# Reading C:/altera/12.1/modelsim_ase/tcl/vsim/pref.tcl 
# do d:/Programming/github/vunit/vunit/vhdl/run/vunit_out/tests/tb_run_lib.tb_run/modelsim/gui_load.do 
# vsim -L vunit_lib -L tb_run_lib -modelsimini d:/Programming/github/vunit/vunit/vhdl/run/vunit_out/modelsim/modelsim.ini -onfinish stop -quiet -t ps -wlf d:/Programming/github/vunit/vunit/vhdl/run/vunit_out/tests/tb_run_lib.tb_run/modelsim/vsim.wlf -g/tb_run/output_path=d:/Programming/github/vunit/vunit/vhdl/run/vunit_out/tests/tb_run_lib.tb_run/ tb_run_lib.tb_run(test_fixture) 
# List of VUnit modelsim commands: 
# vunit_help 
#   - Prints this help 
# vunit_load [vsim_extra_args] 
#   - Load design with correct generics for the test 
#   - Optional first argument are passed as extra flags to vsim 
# vunit_run 
#   - Run test, must do vunit_load first 
examine /run_base_pkg/runner.exit_without_errors
# Z
1 != 0
# invalid command name "1"
{1} != {0}
# invalid command name "1"
expr 1 = 1
# syntax error in expression "1 = 1": extra tokens at end of expression
expr 1 != 1
# 0
expr 1 == 1
# 1
expr Z == 1
# syntax error in expression "Z == 1": variable references require preceding $
expr "Z" == "1"
# syntax error in expression "Z == 1": variable references require preceding $
expr {Z} == {1}
# syntax error in expression "Z == 1": variable references require preceding $
string compare 1 1
# 0
string compare 1 0
# 1
string compare 1 z
# -1
expr 1 eq 2
# 0
expr 1 eq 1
# 1
expr 1 eq z
# syntax error in expression "1 eq z": variable references require preceding $
expr 1 eq {z}
# syntax error in expression "1 eq z": variable references require preceding $
expr 1 eq "z"
# syntax error in expression "1 eq z": variable references require preceding $
expr 1 eq string z
# syntax error in expression "1 eq string z": variable references require preceding $
expr 1 eq [string z]
# bad option "z": must be bytelength, compare, equal, first, index, is, last, length, map, match, range, repeat, replace, tolower, toupper, totitle, trim, trimleft, trimright, wordend, or wordstart
