{ "info": { "author": "XESS Corporation", "author_email": "info@xess.com", "bugtrack_url": null, "classifiers": [ "Development Status :: 2 - Pre-Alpha", "Intended Audience :: Developers", "License :: OSI Approved :: MIT License", "Natural Language :: English", "Programming Language :: Python :: 2", "Programming Language :: Python :: 2.6", "Programming Language :: Python :: 2.7" ], "description": "===============================\nxsconnect\n===============================\n\n.. image:: https://img.shields.io/travis/xesscorp/xsconnect.svg\n :target: https://travis-ci.org/xesscorp/xsconnect\n\n.. image:: https://img.shields.io/pypi/v/xsconnect.svg\n :target: https://pypi.python.org/pypi/xsconnect\n\n\nGenerate pin assignment constraints for a given combination of XESS peripheral + motherboard + daughterboard.\n\n* Free software: MIT license\n* Documentation: https://xesscorp.github.com/xsconnect.\n\nFeatures\n--------\n\n* Automates the tedious process of creating FPGA pin assignments for a given combination\n of XESS FPGA board (e.g. XuLA2), motherboard (e.g. StickIt!) and \n peripheral board (e.g. StickIt! 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