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        "author": "Ciro Santilli",
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        "description": "= vcdvcd\n:idprefix:\n:idseparator: -\n:sectanchors:\n:sectlinks:\n:sectnumlevels: 6\n:sectnums:\n:toc: macro\n:toclevels: 6\n:toc-title:\n\nPython Verilog value change dump (VCD) parser library + the nifty <<vcdcat>> VCD command line viewer.\n\ntoc::[]\n\n== Installation\n\nInstall the latest release:\n\n....\npython -m pip install --user vcdvcd\n....\n\nInstall master directly from this repository:\n\n....\npython -m pip install --editable . --user\n....\n\nUse <<vcdcat>> directly from this repo without installing:\n\n....\n./vcdcat -h\n....\n\n== vcdcat\n\nNifty terminal CLI VCD viewer:\n\n....\n./vcdcat -h\n....\n\nDump all signal values:\n\n....\n./vcdcat counter_tb.vcd\n....\n\nOutput:\n\n....\n0 time\n1 counter_tb.clock\n2 counter_tb.enable\n3 counter_tb.out[1:0]\n4 counter_tb.reset\n5 counter_tb.top.out[1:0]\n\n0 1 2 3 4 5\n===========\n0 1 0 x 0 x\n1 0 0 x 1 x\n2 1 0 0 1 0\n3 0 0 0 0 0\n4 1 0 0 0 0\n5 0 1 0 0 0\n6 1 1 1 0 1\n7 0 1 1 0 1\n8 1 1 2 0 2\n9 0 1 2 0 2\n10 1 1 3 0 3\n11 0 1 3 0 3\n12 1 1 0 0 0\n13 0 1 0 0 0\n14 1 1 1 0 1\n15 0 1 1 0 1\n16 1 1 2 0 2\n17 0 1 2 0 2\n18 1 1 3 0 3\n19 0 1 3 0 3\n20 1 1 0 0 0\n21 0 1 0 0 0\n22 1 1 1 0 1\n23 0 1 1 0 1\n24 1 1 2 0 2\n25 0 0 2 0 2\n....\n\nDump only a some of the signals:\n\n....\n./vcdcat counter_tb.vcd top.enable top.reset\n....\n\nOutput:\n\n....\n0 time\n1 counter_tb.top.enable\n2 counter_tb.top.reset\n\n0 1 2\n=====\n0 0 0\n1 0 1\n3 0 0\n5 1 0\n25 0 0\n....\n\nOnly times for which at least one signal changed are shown.\n\nDump only the signals that changed for each time:\n\n....\n./vcdcat -d counter_tb.vcd\n....\n\nOutput:\n\n....\n0 x counter_tb.top.out[1:0]\n0 0 counter_tb.reset\n0 0 counter_tb.enable\n0 1 counter_tb.clock\n0 x counter_tb.out[1:0]\n1 0 counter_tb.clock\n1 1 counter_tb.reset\n2 0 counter_tb.out[1:0]\n2 0 counter_tb.top.out[1:0]\n2 1 counter_tb.clock\n3 0 counter_tb.clock\n3 0 counter_tb.reset\n4 1 counter_tb.clock\n5 0 counter_tb.clock\n5 1 counter_tb.enable\n6 1 counter_tb.out[1:0]\n6 1 counter_tb.top.out[1:0]\n6 1 counter_tb.clock\n7 0 counter_tb.clock\n8 2 counter_tb.out[1:0]\n8 2 counter_tb.top.out[1:0]\n8 1 counter_tb.clock\n9 0 counter_tb.clock\n10 3 counter_tb.out[1:0]\n10 3 counter_tb.top.out[1:0]\n10 1 counter_tb.clock\n11 0 counter_tb.clock\n12 0 counter_tb.out[1:0]\n12 0 counter_tb.top.out[1:0]\n12 1 counter_tb.clock\n13 0 counter_tb.clock\n14 1 counter_tb.out[1:0]\n14 1 counter_tb.top.out[1:0]\n14 1 counter_tb.clock\n15 0 counter_tb.clock\n16 2 counter_tb.out[1:0]\n16 2 counter_tb.top.out[1:0]\n16 1 counter_tb.clock\n17 0 counter_tb.clock\n18 3 counter_tb.out[1:0]\n18 3 counter_tb.top.out[1:0]\n18 1 counter_tb.clock\n19 0 counter_tb.clock\n20 0 counter_tb.out[1:0]\n20 0 counter_tb.top.out[1:0]\n20 1 counter_tb.clock\n21 0 counter_tb.clock\n22 1 counter_tb.out[1:0]\n22 1 counter_tb.top.out[1:0]\n22 1 counter_tb.clock\n23 0 counter_tb.clock\n24 2 counter_tb.out[1:0]\n24 2 counter_tb.top.out[1:0]\n24 1 counter_tb.clock\n25 0 counter_tb.clock\n25 0 counter_tb.enable\n26 1 counter_tb.clock\n....\n\n== About this repository\n\nThe VCD format is defined by the Verilog standard, and can be generated with `$dumpvars`.\n\nThe entire VCD is parsed at once. For a stream implementation, see: link:https://github.com/GordonMcGregor/vcd_parser[].\n\nForked from Sameer Gauria's version, which is currently only hosted on PyPI with email patches and no public bug tracking: link:https://pypi.python.org/pypi/Verilog_VCD[]. There is also a read-only mirror at: link:https://github.com/zylin/Verilog_VCD[].\n\nLibrary usage examples:\n\n....\n./examples.py\n....\n\n== Release procedure\n\nCreate a tag and push it:\n\n....\ngit tag -a v1.0.1 -m v1.0.1\ngit push --follow-tags\n....\n\nUpdate the `version` field in `setup.py`:\n\n....\nvim setup.py\n....\n\nPush to PyPi:\n\n....\npython -m pip install --user setuptools wheel twine\npython setup.py sdist bdist_wheel\ntwine upload dist/*\nrm -rf build dist *.egg-info\n....\n\n\n",
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