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    "info": {
        "author": "Takumi Sueda",
        "author_email": "puhitaku@gmail.com",
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        "classifiers": [
            "Development Status :: 4 - Beta",
            "Environment :: Console",
            "Intended Audience :: Developers",
            "License :: OSI Approved :: MIT License",
            "Operating System :: OS Independent",
            "Programming Language :: Python",
            "Programming Language :: Python :: 3",
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        "description": "# uint [![CI](https://travis-ci.org/puhitaku/uint.svg?branch=master)](https://travis-ci.org/puhitaku/uint) [![Coverage Status](https://coveralls.io/repos/github/puhitaku/uint/badge.svg?branch=master)](https://coveralls.io/github/puhitaku/uint?branch=master)\n\n*Fixed-width integer and calculation for Python*\n\n```\n$ pip install uint\n```\n\n\n## Fixed-width integers for Python\n\nuint provides two classes: `Uint` and `Int`. They are calculated like `int` but is fixed-width so they behave like ones that you're familiar with ... like in C language.\n\n```\nIn [1]: from uint import Uint, Int\n\nIn [2]: u, i = Uint(0xff, 8), Int(0xff, 8)\n\nIn [3]: u\nOut[3]: <uint8, value=255>\n\nIn [4]: i\nOut[4]: <int8, value=-1>\n\nIn [5]: u << 2 >> 1\nOut[5]: <uint8, value=126>\n\nIn [6]: i << 2 >> 1\nOut[6]: <int8, value=-2>\n```\n\n\nOf course they overflows when you do like:\n\n```\nIn [1]: from uint import Uint, Int\n\nIn [2]: u, i = Uint(0xff, 8), Int(0x7f, 8)\n\nIn [3]: u, i\nOut[3]: (<uint8, value=255>, <int8, value=127>)\n\nIn [4]: u+1, i+1\nOut[4]: (<uint8, value=0>, <int8, value=-128>)\n```\n\n## Register with multiple fields inside\n\nThe original purpose of this package is to reduce labor of calculating \"register values\" in several MCUs and SoCs. See `examples` directory for detailed usage.\n\n```\nIn [1]: from uint import Register\n\nIn [2]: reg = Register('reg')\n\nIn [3]: reg[15:8] = 'f1'\n\nIn [4]: reg[7:0] = 'f2'\n\nIn [5]: reg['f1'] = 0x5A\n\nIn [6]: reg['f2'] = 0x0F\n\nIn [7]: hex(reg.encode())\nOut[7]: '0x5a0f'\n\nIn [8]: reg.decode(0x1234)\n\nIn [9]: reg['f1'].value.wire.hex\nOut[9]: \"8'h12\"\n\nIn [10]: reg['f2'].value.wire.hex\nOut[10]: \"8'h34\"\n```",
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