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        "author": "Stefan Wallentowitz",
        "author_email": "stefan@wallentowitz.de",
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            "License :: OSI Approved :: MIT License",
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        "description": "RISC-V Model\n============\n\nThis is a python model of the RISC-V ISA. It is intended to be a resource for Python-based automated testing and verification.\nIt is under development and not very useful yet, but can be used to generate random assembler code.\n\nDocumentation: https://riscv-python-model.readthedocs.io/en/latest/\n\nQuick Start\n-----------\n\nFirst install it:\n\n::\n\n    pip3 install riscv-model\n\nCreate random assembler sequences\n`````````````````````````````````\n    \nCreate a random assembler sequence:\n\n::\n\n    riscv-random-asm\n    \nYou can tweak the assembler output:\n\n::\n\n    usage: riscv-random-asm [-h]\n                            [-i {add,sub,sll,slt,sltu,xor,srl,sra,or,and,jalr,addi,slti,sltiu,xori,ori,andi,lb,lh,lw,lbu,lhu,slli,srli,srai,sb,sh,sw,beq,bne,blt,bge,bltu,bgeu,lui,auipc,jal}]\n                            [--version]\n                            [N]\n\n    Generate sequence of assembler instructions.\n\n    positional arguments:\n      N                     Number of assembler instructions\n\n    optional arguments:\n      -h, --help            show this help message and exit\n      -i {add,sub,sll,slt,sltu,xor,srl,sra,or,and,jalr,addi,slti,sltiu,xori,ori,andi,lb,lh,lw,lbu,lhu,slli,srli,srai,sb,sh,sw,beq,bne,blt,bge,bltu,bgeu,lui,auipc,jal}\n                            Restrict to instructions\n      --version             Display version\n\nFor example to generate 100 assembler instructions only with ``add``, ``or`` and ``slti`` instructions:\n\n::\n\n    riscv-random-asm 100 -i add -i or -i slti\n\nDisassemble machine code\n````````````````````````\n\nYou can disassemble a machine code to the assembly code on instruction level:\n\n::\n\n    riscv-machinsn-decode hexstring 0x007938b3 0xc9650993\n\nYou can also directly disassemble object files:\n\n::\n\n    riscv-machinsn-decode objfile file.o\n\n\nAutomatically test random assembler sequences\n`````````````````````````````````````````````\n\n``riscv-random-asm-check`` generates random assembler sequences, compiles them, reads back the machine codes and matches them.\nYou can use that to test your compiler, but it is also used as sanity check for riscv-model itself.\n\n::\n\n    riscv-random-asm-check\n\nIt will by default use ``riscv32-unknown-elf-gcc`` and ``riscv32-unknown-elf-objcopy``, but you can configure the tools with ``--compiler`` and ``--objcopy``.\n\nThe automated tests will test all instructions, you can again restrict the number of instructions and the instructions:\n\n::\n\n    riscv-random-asm-check 1000 -i xor\n\nFinally, you can run the checks for the individual instructions seperately (used in combination with the other options:\n\n::\n\n    riscv-random-asm-check -s",
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