{
    "info": {
        "author": "Anna Verkhovskaya",
        "author_email": "verkhovskaya.anna@gmail.com",
        "bugtrack_url": null,
        "classifiers": [
            "Development Status :: 3 - Alpha",
            "Intended Audience :: Developers",
            "License :: OSI Approved :: MIT License",
            "Programming Language :: Python :: 2",
            "Programming Language :: Python :: 2.7",
            "Programming Language :: Python :: 3",
            "Programming Language :: Python :: 3.6",
            "Topic :: Software Development :: Build Tools"
        ],
        "description": "pywire is an easy-to-use Python library for generating VHDL, designed for use with FPGAs. \n\nFeatures:\n- Simple and complex functions\n- BRAM\n- Import components\n- Generate timing files\n\nDoes not support:\n- More than one clock\n\nTo install:\n```python\npip install pywire\n```\n\nExample:\n```python\nfrom pywire import *\n\nx = Signal(1, io=\u201cout\u201d, port=\u201cP7\u201d)\ny = Signal(1, io=\u201cin\u201d, port=\u201cP42\u201d)\n\ndef inverter(x):\n\treturn 1-x\n\nx.drive(inverter, y)\nprint(vhdl(globals()))\n```\n\nThe full documentation can be found at http://pywire.readthedocs.io/en/latest/",
        "description_content_type": null,
        "docs_url": null,
        "download_url": "",
        "downloads": {
            "last_day": -1,
            "last_month": -1,
            "last_week": -1
        },
        "home_page": "https://github.com/Verkhovskaya/Pywire",
        "keywords": "vhdl fpga",
        "license": "",
        "maintainer": "",
        "maintainer_email": "",
        "name": "pywire",
        "package_url": "https://pypi.org/project/pywire/",
        "platform": "",
        "project_url": "https://pypi.org/project/pywire/",
        "project_urls": {
            "Homepage": "https://github.com/Verkhovskaya/Pywire"
        },
        "release_url": "https://pypi.org/project/pywire/1.0.0/",
        "requires_dist": null,
        "requires_python": "",
        "summary": "A library for generating VHDL, designed for use in FPGAs",
        "version": "1.0.0"
    },
    "last_serial": 3572800,
    "releases": {
        "1.0.0": [
            {
                "comment_text": "",
                "digests": {
                    "md5": "97de8b3b06e0115a1c5439b2f3c899e4",
                    "sha256": "b636a91a8de6c32366f708d030ac695536ccb5f967a06c5d054e708117d23cfa"
                },
                "downloads": -1,
                "filename": "pywire-1.0.0.tar.gz",
                "has_sig": false,
                "md5_digest": "97de8b3b06e0115a1c5439b2f3c899e4",
                "packagetype": "sdist",
                "python_version": "source",
                "requires_python": null,
                "size": 27339,
                "upload_time": "2018-02-11T20:26:10",
                "url": "https://files.pythonhosted.org/packages/d8/b1/ee201fa13d03996e6004777c2ebee146e9be1735f71873a3772ffb131bf8/pywire-1.0.0.tar.gz"
            }
        ]
    },
    "urls": [
        {
            "comment_text": "",
            "digests": {
                "md5": "97de8b3b06e0115a1c5439b2f3c899e4",
                "sha256": "b636a91a8de6c32366f708d030ac695536ccb5f967a06c5d054e708117d23cfa"
            },
            "downloads": -1,
            "filename": "pywire-1.0.0.tar.gz",
            "has_sig": false,
            "md5_digest": "97de8b3b06e0115a1c5439b2f3c899e4",
            "packagetype": "sdist",
            "python_version": "source",
            "requires_python": null,
            "size": 27339,
            "upload_time": "2018-02-11T20:26:10",
            "url": "https://files.pythonhosted.org/packages/d8/b1/ee201fa13d03996e6004777c2ebee146e9be1735f71873a3772ffb131bf8/pywire-1.0.0.tar.gz"
        }
    ]
}