{ "info": { "author": "Shinya Takamaeda-Yamazaki", "author_email": "", "bugtrack_url": null, "classifiers": [], "description": "Pyverilog\n=========\n\n|Build Status|\n\nPython-based Hardware Design Processing Toolkit for Verilog HDL\n\nCopyright 2013, Shinya Takamaeda-Yamazaki\n\nLicense\n=======\n\nApache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)\n\nNote that this software package includes PLY-3.4 in \u201cvparser/ply\u201d. The\nlicense of PLY is BSD.\n\nPublication\n===========\n\nIf you use Pyverilog in your research, please cite my paper.\n\n- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design\n Processing Toolkit for Verilog HDL, 11th International Symposium on\n Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes\n in Computer Science, Vol.9040/2015, pp.451-460, April 2015.\n `Paper `__\n\n::\n\n @inproceedings{Takamaeda:2015:ARC:Pyverilog,\n title={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL},\n author={Takamaeda-Yamazaki, Shinya},\n booktitle={Applied Reconfigurable Computing},\n month={Apr},\n year={2015},\n pages={451-460},\n volume={9040},\n series={Lecture Notes in Computer Science},\n publisher={Springer International Publishing},\n doi={10.1007/978-3-319-16214-0_42},\n url={http://dx.doi.org/10.1007/978-3-319-16214-0_42},\n }\n\nWhat\u2019s Pyverilog?\n=================\n\nPyverilog is an open-source hardware design processing toolkit for\nVerilog HDL. All source codes are written in Python.\n\nPyverilog includes **(1) code parser, (2) dataflow analyzer, (3)\ncontrol-flow analyzer and (4) code generator**. You can create your own\ndesign analyzer, code translator and code generator of Verilog HDL based\non this toolkit.\n\nInstallation\n============\n\nRequirements\n------------\n\n- Python3: 3.6 or later\n\n- Icarus Verilog: 10.1 or later\n\n::\n\n sudo apt install iverilog\n\n- Jinja2: 2.10 or later\n- pytest: 3.2 or later\n- pytest-pythonpath: 0.7 or later\n\n::\n\n pip3 install jinja2 pytest pytest-pythonpath\n\nOptions\n-------\n\n- Graphviz: 2.38.0 or later\n- Pygraphviz: 1.3.1 or later\n\nThese softwares are required for graph visualization by\ndataflow/graphgen.py and controlflow/controlflow_analyzer.py.\n\n::\n\n sudo apt install graphviz\n pip3 install pygraphviz\n\nInstall\n-------\n\nInstall Pyverilog:\n\n::\n\n python3 setup.py install\n\nTools\n=====\n\nThis software includes various tools for Verilog HDL design.\n\n- vparser: Code parser to generate AST (Abstract Syntax Tree) from\n source codes of Verilog HDL.\n- dataflow: Dataflow analyzer with an optimizer to remove redundant\n expressions and some dataflow handling tools.\n- controlflow: Control-flow analyzer with condition analyzer that\n identify when a signal is activated.\n- ast_code_generator: Verilog HDL code generator from AST.\n\nGetting Started\n===============\n\nFirst, please prepare a Verilog HDL source file as below. The file name\nis \u2018test.v\u2019. This sample design adds the input value internally whtn the\nenable signal is asserted. Then is outputs its partial value to the LED.\n\n.. code:: verilog\n\n module top\n (\n input CLK, \n input RST,\n input enable,\n input [31:0] value,\n output [7:0] led\n );\n reg [31:0] count;\n reg [7:0] state;\n assign led = count[23:16];\n always @(posedge CLK) begin\n if(RST) begin\n count <= 0;\n state <= 0;\n end else begin\n if(state == 0) begin\n if(enable) state <= 1;\n end else if(state == 1) begin\n state <= 2;\n end else if(state == 2) begin\n count <= count + value;\n state <= 0;\n end\n end\n end\n endmodule\n\nCode parser\n-----------\n\nLet\u2019s try syntax analysis. Please type the command as below.\n\n::\n\n python3 pyverilog/examples/example_parser.py test.v\n\nThen you got the result as below. The result of syntax analysis is\ndisplayed.\n\n::\n\n Source: (at 1)\n Description: (at 1)\n ModuleDef: top (at 1)\n Paramlist: (at 0)\n Portlist: (at 2)\n Ioport: (at 3)\n Input: CLK, False (at 3)\n Ioport: (at 4)\n Input: RST, False (at 4)\n Ioport: (at 5)\n Input: enable, False (at 5)\n Ioport: (at 6)\n Input: value, False (at 6)\n Width: (at 6)\n IntConst: 31 (at 6)\n IntConst: 0 (at 6)\n Ioport: (at 7)\n Output: led, False (at 7)\n Width: (at 7)\n IntConst: 7 (at 7)\n IntConst: 0 (at 7)\n Decl: (at 9)\n Reg: count, False (at 9)\n Width: (at 9)\n IntConst: 31 (at 9)\n IntConst: 0 (at 9)\n Decl: (at 10)\n Reg: state, False (at 10)\n Width: (at 10)\n IntConst: 7 (at 10)\n IntConst: 0 (at 10)\n Assign: (at 11)\n Lvalue: (at 11)\n Identifier: led (at 11)\n Rvalue: (at 11)\n Partselect: (at 11)\n Identifier: count (at 11)\n IntConst: 23 (at 11)\n IntConst: 16 (at 11)\n Always: (at 12)\n SensList: (at 12)\n Sens: posedge (at 12)\n Identifier: CLK (at 12)\n Block: None (at 12)\n IfStatement: (at 13)\n Identifier: RST (at 13)\n Block: None (at 13)\n NonblockingSubstitution: (at 14)\n Lvalue: (at 14)\n Identifier: count (at 14)\n Rvalue: (at 14)\n IntConst: 0 (at 14)\n NonblockingSubstitution: (at 15)\n Lvalue: (at 15)\n Identifier: state (at 15)\n Rvalue: (at 15)\n IntConst: 0 (at 15)\n Block: None (at 16)\n IfStatement: (at 17)\n Eq: (at 17)\n Identifier: state (at 17)\n IntConst: 0 (at 17)\n Block: None (at 17)\n IfStatement: (at 18)\n Identifier: enable (at 18)\n NonblockingSubstitution: (at 18)\n Lvalue: (at 18)\n Identifier: state (at 18)\n Rvalue: (at 18)\n IntConst: 1 (at 18)\n IfStatement: (at 19)\n Eq: (at 19)\n Identifier: state (at 19)\n IntConst: 1 (at 19)\n Block: None (at 19)\n NonblockingSubstitution: (at 20)\n Lvalue: (at 20)\n Identifier: state (at 20)\n Rvalue: (at 20)\n IntConst: 2 (at 20)\n IfStatement: (at 21)\n Eq: (at 21)\n Identifier: state (at 21)\n IntConst: 2 (at 21)\n Block: None (at 21)\n NonblockingSubstitution: (at 22)\n Lvalue: (at 22)\n Identifier: count (at 22)\n Rvalue: (at 22)\n Plus: (at 22)\n Identifier: count (at 22)\n Identifier: value (at 22)\n NonblockingSubstitution: (at 23)\n Lvalue: (at 23)\n Identifier: state (at 23)\n Rvalue: (at 23)\n IntConst: 0 (at 23)\n\nDataflow analyzer\n-----------------\n\nLet\u2019s try dataflow analysis. Please type the command as below.\n\n::\n\n python3 pyverilog/examples/example_dataflow_analyzer.py -t top test.v \n\nThen you got the result as below. The result of each signal definition\nand each signal assignment are displayed.\n\n::\n\n Directive:\n Instance:\n (top, 'top')\n Term:\n (Term name:top.led type:{'Output'} msb:(IntConst 7) lsb:(IntConst 0))\n (Term name:top.enable type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))\n (Term name:top.CLK type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))\n (Term name:top.count type:{'Reg'} msb:(IntConst 31) lsb:(IntConst 0))\n (Term name:top.state type:{'Reg'} msb:(IntConst 7) lsb:(IntConst 0))\n (Term name:top.RST type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))\n (Term name:top.value type:{'Input'} msb:(IntConst 31) lsb:(IntConst 0))\n Bind:\n (Bind dest:top.count tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(Operator Plus Next:(Terminal top.count),(Terminal top.value)))))))\n (Bind dest:top.state tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) True:(Branch Cond:(Terminal top.enable) True:(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) True:(IntConst 2) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(IntConst 0))))))\n (Bind dest:top.led tree:(Partselect Var:(Terminal top.count) MSB:(IntConst 23) LSB:(IntConst 16)))\n\nLet\u2019s view the result of dataflow analysis as a picture file. Now we\nselect \u2018led\u2019 as the target. Please type the command as below. In this\nexample, Graphviz and Pygraphviz are installed.\n\n::\n\n python3 pyverilog/examples/example_graphgen.py -t top -s top.led test.v \n\nThen you got a png file (out.png). The picture shows that the definition\nof \u2018led\u2019 is a part-selection of \u2018count\u2019 from 23-bit to 16-bit.\n\n.. figure:: img/out.png\n :alt: out.png\n\n out.png\n\nControl-flow analyzer\n---------------------\n\nLet\u2019s try control-flow analysis. Please type the command as below. In\nthis example, Graphviz and Pygraphviz are installed. If don\u2019t use\nGraphviz, please append \u201c\u2013nograph\u201d option.\n\n::\n\n python3 pyverilog/examples/example_controlflow_analyzer.py -t top test.v \n\nThen you got the result as below. The result shows that the state\nmachine structure and transition conditions to the next state in the\nstate machine.\n\n::\n\n FSM signal: top.count, Condition list length: 4\n FSM signal: top.state, Condition list length: 5\n Condition: (Ulnot, Eq), Inferring transition condition\n Condition: (Eq, top.enable), Inferring transition condition\n Condition: (Ulnot, Ulnot, Eq), Inferring transition condition\n # SIGNAL NAME: top.state\n # DELAY CNT: 0\n 0 --(top_enable>'d0)--> 1\n 1 --None--> 2\n 2 --None--> 0\n Loop\n (0, 1, 2)\n\nYou got also a png file (top_state.png), if you did not append\n\u201c\u2013nograph\u201d. The picture shows that the graphical structure of the state\nmachine.\n\n.. figure:: img/top_state.png\n :alt: top_state.png\n\n top_state.png\n\nCode generator\n--------------\n\nFinally, let\u2019s try code generation. Please prepare a Python script as\nbelow. The file name is \u2018test.py\u2019. A Verilog HDL code is represented by\nusing the AST classes defined in \u2018vparser.ast\u2019.\n\n.. code:: python\n\n from __future__ import absolute_import\n from __future__ import print_function\n import sys\n import os\n import pyverilog.vparser.ast as vast\n from pyverilog.ast_code_generator.codegen import ASTCodeGenerator\n\n def main():\n datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )\n params = vast.Paramlist( [datawid] )\n clk = vast.Ioport( vast.Input('CLK') )\n rst = vast.Ioport( vast.Input('RST') )\n width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )\n led = vast.Ioport( vast.Output('led', width=width) )\n ports = vast.Portlist( [clk, rst, led] )\n\n width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )\n count = vast.Reg('count', width=width)\n\n assign = vast.Assign(\n vast.Lvalue(vast.Identifier('led')), \n vast.Rvalue(\n vast.Partselect(\n vast.Identifier('count'), # count\n vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:\n vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]\n\n sens = vast.Sens(vast.Identifier('CLK'), type='posedge')\n senslist = vast.SensList([ sens ])\n\n assign_count_true = vast.NonblockingSubstitution(\n vast.Lvalue(vast.Identifier('count')),\n vast.Rvalue(vast.IntConst('0')))\n if0_true = vast.Block([ assign_count_true ])\n\n # count + 1\n count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))\n assign_count_false = vast.NonblockingSubstitution(\n vast.Lvalue(vast.Identifier('count')),\n vast.Rvalue(count_plus_1))\n if0_false = vast.Block([ assign_count_false ])\n\n if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)\n statement = vast.Block([ if0 ])\n\n always = vast.Always(senslist, statement)\n\n items = []\n items.append(count)\n items.append(assign)\n items.append(always)\n\n ast = vast.ModuleDef(\"top\", params, ports, items)\n \n codegen = ASTCodeGenerator()\n rslt = codegen.visit(ast)\n print(rslt)\n\n if __name__ == '__main__':\n main()\n\nPlease type the command as below at the same directory with Pyverilog.\n\n::\n\n python3 test.py\n\nThen Verilog HDL code generated from the AST instances is displayed.\n\n.. code:: verilog\n\n module top #\n (\n parameter DATAWID = 32\n )\n (\n input CLK,\n input RST,\n output [7:0] led\n );\n\n reg [DATAWID-1:0] count;\n assign led = count[DATAWID-1:DATAWID-8];\n\n always @(posedge CLK) begin\n if(RST) begin\n count <= 0;\n end else begin\n count <= count + 1;\n end\n end\n\n\n endmodule\n\nRelated Project and Site\n========================\n\n`Veriloggen `__ - A library for\nconstructing a Verilog HDL source code in Python\n\n`IPgen `__ - IP-core package generator\nfor AXI4/Avalon\n\n`PyCoRAM `__ - Python-based Portable\nIP-core Synthesis Framework for FPGA-based Computing\n\n`flipSyrup `__ - Cycle-Accurate\nHardware Simulation Framework on Abstract FPGA Platforms\n\n`Pyverilog_toolbox `__ -\nPyverilog_toolbox is Pyverilog-based verification/design tool, which is\ndeveloped by Fukatani-san and uses Pyverilog as a fundamental library.\nThanks for your contribution!\n\n`shtaxxx.hatenablog.com `__\n- Blog entry for introduction and examples of Pyverilog (in Japansese)\n\n.. |Build Status| image:: https://travis-ci.org/PyHDI/Pyverilog.svg\n :target: https://travis-ci.org/PyHDI/Pyverilog", "description_content_type": "", "docs_url": null, "download_url": "", "downloads": { "last_day": -1, "last_month": -1, "last_week": -1 }, "home_page": "https://github.com/PyHDI/Pyverilog", "keywords": "Verilog HDL,Lexer,Parser,Dataflow Analyzer,Control-flow Analyzer,Code Generator,Visualizer", "license": "Apache License 2.0", "maintainer": "", "maintainer_email": "", "name": "pyverilog", "package_url": "https://pypi.org/project/pyverilog/", "platform": "", "project_url": "https://pypi.org/project/pyverilog/", "project_urls": { "Homepage": "https://github.com/PyHDI/Pyverilog" }, "release_url": "https://pypi.org/project/pyverilog/1.1.4/", "requires_dist": null, "requires_python": "", "summary": "Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator", "version": "1.1.4" }, "last_serial": 5007385, "releases": { "0.9.1": [ { "comment_text": "", "digests": { "md5": "9856879f96616de42a80775c3c6c0ab5", "sha256": "2bebce94d6164498d3dd0cb141b102c000c1cca1a9d3ec393bd8675e9ed4ff2c" }, "downloads": -1, "filename": "pyverilog-0.9.1.tar.gz", "has_sig": false, "md5_digest": "9856879f96616de42a80775c3c6c0ab5", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 117607, "upload_time": "2014-11-10T11:25:46", "url": "https://files.pythonhosted.org/packages/ab/8e/4f0b3ddd145dba52062041b0aa5c602b622cbd36f9fa8afc4d44c2087d28/pyverilog-0.9.1.tar.gz" } ], "0.9.2": [ { "comment_text": "", "digests": { "md5": "19a3a6a192982cf9a3d9e771e74a483f", "sha256": "02aad9bd44affe436ce52976b27931ad0ba43c09cb21a612b508557c736341f8" }, "downloads": -1, "filename": "pyverilog-0.9.2.tar.gz", "has_sig": false, "md5_digest": "19a3a6a192982cf9a3d9e771e74a483f", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 118856, "upload_time": "2015-02-07T04:51:12", "url": "https://files.pythonhosted.org/packages/4e/37/385ad837e527de66d6667bd1fa4090bdf002dd306f991a683302a229ce9a/pyverilog-0.9.2.tar.gz" } ], "0.9.3": [ { "comment_text": "", "digests": { "md5": "463c213425faa8eea7c6a7ca9a78fe8b", "sha256": "5cd2d06a855ba684ee5c9089b467e3460e9c945bb58a0596e53519e25b2963f2" }, "downloads": -1, "filename": "pyverilog-0.9.3.tar.gz", "has_sig": false, "md5_digest": "463c213425faa8eea7c6a7ca9a78fe8b", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 123309, "upload_time": "2015-05-23T02:06:32", "url": "https://files.pythonhosted.org/packages/7a/a6/6d1e8d78bf82b870ba5734602d6b0792837e55f3aded4bff0f5f3ef302a9/pyverilog-0.9.3.tar.gz" } ], "0.9.5": [ { "comment_text": "", "digests": { "md5": "5ff6c87e3fca9a636116376fa3bc9251", "sha256": "4b88f15d575d9e1663a6883837bed65b0286c9fa1df6eb9b6603be8fe01734c7" }, "downloads": -1, "filename": "pyverilog-0.9.5.tar.gz", "has_sig": false, "md5_digest": "5ff6c87e3fca9a636116376fa3bc9251", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 124121, "upload_time": "2015-06-21T16:59:04", "url": "https://files.pythonhosted.org/packages/46/60/a91affae8d1affd79b20531f80464e74434a0ed870b3369d3d70c70e524a/pyverilog-0.9.5.tar.gz" } ], "0.9.6": [ { "comment_text": "", "digests": { "md5": "1221113d4904973da10d7e6653ac041a", "sha256": "cdb36aee241e6b1f17101a4a9008fad9cd98cbad72b2d55f4718083439a3e90b" }, "downloads": -1, "filename": "pyverilog-0.9.6.tar.gz", "has_sig": false, "md5_digest": "1221113d4904973da10d7e6653ac041a", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 121159, "upload_time": "2015-08-18T18:05:50", "url": "https://files.pythonhosted.org/packages/2e/32/bc4847b323cefd360f27ad7496f800ea21da4cb8bcabdec4af31304a4120/pyverilog-0.9.6.tar.gz" } ], "1.0.0": [ { "comment_text": "", "digests": { "md5": "a70fc0c45d626607c11eeb59d817c633", "sha256": "2d45c39f077653f27af2bb8a2a829a0ad19f287f8676814965b012b2f1eb79c2" }, "downloads": -1, "filename": "pyverilog-1.0.0.tar.gz", "has_sig": false, "md5_digest": "a70fc0c45d626607c11eeb59d817c633", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 300270, "upload_time": "2015-10-29T11:17:19", "url": "https://files.pythonhosted.org/packages/36/53/21604ae9985ec4a61feb4702859fe22e243c463891fa035946e929dc8ffc/pyverilog-1.0.0.tar.gz" } ], "1.0.1": [ { "comment_text": "", "digests": { "md5": "b15349ecbac9e0a050ec4010579c3675", "sha256": "333614df9300bd15d6d33f915c6090bff1cfcb38a646e1ffb10d3e68be368a09" }, "downloads": -1, "filename": "pyverilog-1.0.1.tar.gz", "has_sig": false, "md5_digest": "b15349ecbac9e0a050ec4010579c3675", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 298249, "upload_time": "2015-10-31T17:37:02", "url": "https://files.pythonhosted.org/packages/86/72/de80d0b2ad711c555f1b02391a2d2828a385c94bbad2e1851d69d4e231b3/pyverilog-1.0.1.tar.gz" } ], "1.0.2": [ { "comment_text": "", "digests": { "md5": "16a774b636ebe642ea80a0f729931779", "sha256": "eaf6f7af10b644bb5ed413cae63bdfe06e55886277b43937e343ae2bf302455d" }, "downloads": -1, "filename": "pyverilog-1.0.2.tar.gz", "has_sig": false, "md5_digest": "16a774b636ebe642ea80a0f729931779", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 158317, "upload_time": "2015-11-19T19:07:10", "url": "https://files.pythonhosted.org/packages/53/14/14d7a63f0a32f157d8663fe576f4c3f3ec7a30de468be03d9f9ec27f5c80/pyverilog-1.0.2.tar.gz" } ], "1.0.3": [ { "comment_text": "", "digests": { "md5": "761efd2ebdffaffb0c82961f2117cc28", "sha256": "798bc84f6fd3bc0264418d9234768e28bf26ec2277ba5d979b764d79aeff290c" }, "downloads": -1, "filename": "pyverilog-1.0.3.tar.gz", "has_sig": false, "md5_digest": "761efd2ebdffaffb0c82961f2117cc28", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 158472, "upload_time": "2015-11-21T16:46:04", "url": "https://files.pythonhosted.org/packages/52/b1/ce14c26de507c5655798ae65aea0747b1a64717798a184c968a211e91133/pyverilog-1.0.3.tar.gz" } ], "1.0.4": [ { "comment_text": "", "digests": { "md5": "ac7cb9df18a70b238a5644ba9fb9229b", "sha256": "7c211b665aac6cd8f9df42aea5afc4b46113b0d49d5d0878bdf6919bf230e3d9" }, "downloads": -1, "filename": "pyverilog-1.0.4.tar.gz", "has_sig": false, "md5_digest": "ac7cb9df18a70b238a5644ba9fb9229b", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 160377, "upload_time": "2015-11-22T15:03:30", "url": "https://files.pythonhosted.org/packages/25/0b/5a886f7b3e34c5240b1268bbeaf7937d25d2c2273223b913b028251971a0/pyverilog-1.0.4.tar.gz" } ], "1.0.5": [ { "comment_text": "", "digests": { "md5": "3289641b3c47fa0cf4364b68aa911f99", "sha256": "603ff0e5f838718aca51a2e003e9e0fa113cde219fb6b90044df01f29eb70124" }, "downloads": -1, "filename": "pyverilog-1.0.5.tar.gz", "has_sig": false, "md5_digest": "3289641b3c47fa0cf4364b68aa911f99", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 160828, "upload_time": "2016-01-18T05:48:11", "url": "https://files.pythonhosted.org/packages/02/f6/50a50b3f9522af3721eba0cb30ce1ac2207a2c80f861531889512ed65262/pyverilog-1.0.5.tar.gz" } ], "1.0.6": [ { "comment_text": "", "digests": { "md5": "58aa6898d572505080e4317fe1dc1e4e", "sha256": "c1378b7e0b0dc8a8c2dee9f869abf4fdc65bff171a959600c10cf11350452aee" }, "downloads": -1, "filename": "pyverilog-1.0.6.tar.gz", "has_sig": false, "md5_digest": "58aa6898d572505080e4317fe1dc1e4e", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 160875, "upload_time": "2016-01-21T09:13:41", "url": "https://files.pythonhosted.org/packages/bd/c4/7ca905b8af670fda005be466d54ec730e270d7935e734f6c0186ac914d89/pyverilog-1.0.6.tar.gz" } ], "1.0.7": [ { "comment_text": "", "digests": { "md5": "02ba863c378913eff20b3db16d70e4e1", "sha256": "70ab9ba6104c9d75c1b82d6b34a9c7b9f26c70f22c52127c571d9ee10dcd72d5" }, "downloads": -1, "filename": "pyverilog-1.0.7.tar.gz", "has_sig": false, "md5_digest": "02ba863c378913eff20b3db16d70e4e1", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 161858, "upload_time": "2017-04-07T12:27:48", "url": "https://files.pythonhosted.org/packages/6c/d0/cfe44f0250b24e5f7dbd28e4fa17d9d1fab0b876eaa9ce7b1a3c3953041a/pyverilog-1.0.7.tar.gz" } ], "1.0.8": [ { "comment_text": "", "digests": { "md5": "b802a3b9613b177861350d2285dad55f", "sha256": "12539b4c72bda452cabeb65ba1e830edb22dce40ad16713b0d55dc67526bccb8" }, "downloads": -1, "filename": "pyverilog-1.0.8.tar.gz", "has_sig": false, "md5_digest": "b802a3b9613b177861350d2285dad55f", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 161935, "upload_time": "2017-04-10T04:18:46", "url": "https://files.pythonhosted.org/packages/c9/fb/ee0f9efafad227f912113e321502f679a965509a7f5bb6822807e1c19f80/pyverilog-1.0.8.tar.gz" } ], "1.0.9": [ { "comment_text": "", "digests": { "md5": "c1423f374440e372e69ae381310d9653", "sha256": "aede564aa04eefb0b04e4aaf3575ae5a97eb74df86cc4c3dcd44fad15d4ae66f" }, "downloads": -1, "filename": "pyverilog-1.0.9.tar.gz", "has_sig": false, "md5_digest": "c1423f374440e372e69ae381310d9653", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 162240, "upload_time": "2017-05-02T15:44:50", "url": "https://files.pythonhosted.org/packages/8d/c2/c2ead1ec11ff2b3f9b7b8fd98be439c427b32709cf52d7cb027e26a3a423/pyverilog-1.0.9.tar.gz" } ], "1.1.0": [ { "comment_text": "", "digests": { "md5": "e6f85f31c2a97725167a4649afbe642a", "sha256": "f3a24865439d371cc65680600b46177aefa9e0819ca817e01fb521b4273a0dc9" }, "downloads": -1, "filename": "pyverilog-1.1.0.tar.gz", "has_sig": false, "md5_digest": "e6f85f31c2a97725167a4649afbe642a", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 162153, "upload_time": "2017-10-01T03:06:25", "url": "https://files.pythonhosted.org/packages/1a/a1/f313d58520decba985b3c0272696a64d790ee2b84971b21baa81c1b2c529/pyverilog-1.1.0.tar.gz" } ], "1.1.1": [ { "comment_text": "", "digests": { "md5": "8030036d86634cf0d808a1b67e857e45", "sha256": "fcb40db21aa53ec675f1b51517856854c54c1ba47037c5e3436d74b082032f15" }, "downloads": -1, "filename": "pyverilog-1.1.1.tar.gz", "has_sig": false, "md5_digest": "8030036d86634cf0d808a1b67e857e45", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 162335, "upload_time": "2017-10-04T14:03:16", "url": "https://files.pythonhosted.org/packages/ff/0b/3f98db8d77e315fa00c30445bd30b188148f958cb2a19f36ae2d42205183/pyverilog-1.1.1.tar.gz" } ], "1.1.2": [ { "comment_text": "", "digests": { "md5": "48e5cd6a80ed72987542ede575b1fff3", "sha256": "1efa541b9a70b529b5ca6576ac24c65142865040b619f664dd235c053c06cade" }, "downloads": -1, "filename": "pyverilog-1.1.2.tar.gz", "has_sig": false, "md5_digest": "48e5cd6a80ed72987542ede575b1fff3", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 161094, "upload_time": "2018-07-01T15:09:03", "url": "https://files.pythonhosted.org/packages/bc/cb/859d4925db309fc91f6219b6ae007c3061a05f39645c97698358c5f02c89/pyverilog-1.1.2.tar.gz" } ], "1.1.3": [ { "comment_text": "", "digests": { "md5": "81a3b24f8269fe7c4bf8855793cea3c3", "sha256": "495506aa574df7dceae95702e534b0b3fc9b0402ca3b54a4cfc00bff8fa1097b" }, "downloads": -1, "filename": "pyverilog-1.1.3.tar.gz", "has_sig": false, "md5_digest": "81a3b24f8269fe7c4bf8855793cea3c3", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 161032, "upload_time": "2018-11-25T03:34:52", "url": "https://files.pythonhosted.org/packages/99/7b/70e4d049fed21d7c8f1b9d8239398a412ae620a7295aafb449cb2c1d7f91/pyverilog-1.1.3.tar.gz" } ], "1.1.4": [ { "comment_text": "", "digests": { "md5": "d7fca28cee521722d815a56f6933e9e1", "sha256": "f16d44db281e6ae5f20b14ca5170d63da7cbba3954b5210241886825f92ab74c" }, "downloads": -1, "filename": "pyverilog-1.1.4.tar.gz", "has_sig": false, "md5_digest": "d7fca28cee521722d815a56f6933e9e1", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 166268, "upload_time": "2019-03-30T15:52:34", "url": "https://files.pythonhosted.org/packages/c8/b1/9bd389bab35fe2d8669eabed10113d5aff7a78ebf13f193d194a2e09161c/pyverilog-1.1.4.tar.gz" } ] }, "urls": [ { "comment_text": "", "digests": { "md5": "d7fca28cee521722d815a56f6933e9e1", "sha256": "f16d44db281e6ae5f20b14ca5170d63da7cbba3954b5210241886825f92ab74c" }, "downloads": -1, "filename": "pyverilog-1.1.4.tar.gz", "has_sig": false, "md5_digest": "d7fca28cee521722d815a56f6933e9e1", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 166268, "upload_time": "2019-03-30T15:52:34", "url": "https://files.pythonhosted.org/packages/c8/b1/9bd389bab35fe2d8669eabed10113d5aff7a78ebf13f193d194a2e09161c/pyverilog-1.1.4.tar.gz" } ] }