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        "author": "David Craven",
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        "description": "[![Build Status](https://travis-ci.org/dvc94ch/pykicad.svg?branch=master)](https://travis-ci.org/dvc94ch/pykicad)\n\n# Routines for generating and parsing KiCAD files\n\nThere are multiple python scripts that read and write kicad file\nformats. Currently there is the problem that each project reimplements\nbasic parsing and serialization of these formats.\n\nThe aim of this project is to provide high quality and well tested\nformat support so that other projects can focus on the interesting\nstuff.\n\n## Status\nComplete support for the kicad_pcb and kicad_mod formats.  The schemas of the\nclasses should provide good documentation on the kicad file format.  A summary\nof all methods and fields can be found in the section API docs.\n\n## Usage\n```python\nfrom numpy import array\nfrom pykicad.pcb import *\nfrom pykicad.module import *\n\n# Define nets\nvi, vo, gnd = Net('VI'), Net('VO'), Net('GND')\n\n# Load footprints\nr1 = Module.from_library('Resistors_SMD', 'R_0805')\nr2 = Module.from_library('Resistors_SMD', 'R_0805')\n\n# Connect pads\nr1.pads[0].net = vi\nr1.pads[1].net = vo\nr2.pads[0].net = vo\nr2.pads[1].net = gnd\n\n# Place components\nr1.at = [0, 0]\nr2.at = [5, 0]\n\n# Compute positions\nstart = array(r1.pads[1].at) + array(r1.at)\nend = array(r2.pads[0].at) + array(r2.at)\npos = start + (end - start) / 2\n\n# Create vias\nv1 = Via(at=pos.tolist(), size=.8, drill=.6, net=vo.code)\n\n# Create segments\ns1 = Segment(start=start.tolist(), end=pos.tolist(), net=vo.code)\ns2 = Segment(start=pos.tolist(), end=end.tolist(), net=vo.code)\n\n# Create zones\ncoords = [(0, 0), (10, 0), (10, 10), (0, 10)]\ngndplane_top = Zone(net_name='GND', layer='F.Cu', polygon=coords, clearance=0.3)\n\n\nlayers = [\n    Layer('F.Cu'),\n    Layer('Inner1.Cu'),\n    Layer('Inner2.Cu'),\n    Layer('B.Cu'),\n    Layer('Edge.Cuts', type='user')\n]\n\nfor layer in ['Mask', 'Paste', 'SilkS', 'CrtYd', 'Fab']:\n    for side in ['B', 'F']:\n        layers.append(Layer('%s.%s' % (side, layer), type='user'))\n\nnc1 = NetClass('default', trace_width=1, nets=['VI', 'VO', 'GND'])\n\n# Create PCB\npcb = Pcb()\npcb.title = 'A title'\npcb.comment1 = 'Comment 1'\npcb.page_type = [20, 20]\npcb.num_nets = 5\npcb.setup = Setup(grid_origin=[10, 10])\npcb.layers = layers\npcb.modules += [r1, r2]\npcb.net_classes += [nc1]\npcb.nets += [vi, vo, gnd]\npcb.segments += [s1, s2]\npcb.vias += [v1]\npcb.zones += [gndplane_top]\n\npcb.to_file('project')\n```\n\n\n## Supported file formats\n\n* Modules (*.pretty, *.kicad_mod) in module.py\n* Pcbnew (*.kicad_pcb) in pcb.py\n\n\n# API docs\n## modules.py\n### Classes\n* Module(name, version, locked, placed, layer, tedit, tstamp, at, descr, tags,\n         path, attr, autoplace_cost90, autoplace_cost180, solder_mask_margin,\n         solder_paste_margin, solder_paste_ratio, clearance, zone_connect,\n         thermal_width, thermal_gap, texts, lines, circles, arcs, curves,\n         polygons, pads, models)\n  * pads_by_name(name)\n  * set_reference(name)\n  * set_value(value)\n  * geometry()\n  * elements_by_layer(layer)\n  * courtyard()\n  * place(x, y)\n  * rotate(angle)\n  * connect(pad, net)\n  * flip()\n  * from_file(cls, path)\n  * from_library(cls, lib, name)\n* Pad(name, type, shape, size, at, rect_delta, roundrect_rratio, drill, layers,\n      net, die_length, solder_mask_margin, solder_paste_margin, solder_paste_margin_ratio,\n      clearance, zone_connect)\n  * rotate(angle)\n  * flip()\n* Drill(size, offset)\n* Net(code, name)\n* Model(path, at, scale, rotate)\n* Text(type, text, at, layer, size, thickness, bold, italic, justify, hide, tstamp)\n  * rotate(angle)\n  * flip()\n* Line(start, end, layer, width, tstamp, status)\n  * flip()\n* Circle(center, end, layer, width, tstamp, status)\n  * flip()\n* Arc(start, end, angle, layer, width, tstamp, status)\n  * flip()\n* Polygon(pts, layer, width, tstamp, status)\n  * flip()\n* Curve(start, bezier1, bezier2, end, layer, width, tstamp, status)\n  * flip()\n\n## pcb.py\n### Classes\n* Pcb(version, host, board_thickness, num_nets, num_no_connects, title, date, rev,\n      company, comment1, comment2, comment3, comment4, page_type, portrait,\n      setup, layers, nets, net_classes, modules, segments, vias, texts, lines,\n      arcs, circles, polygons, curves, zones, targets, dimensions)\n  * geometry()\n  * elements_by_layer(layer)\n  * outline()\n  * module_by_reference(name)\n  * net_by_code(code)\n  * to_file(path)\n  * from_file(cls, path)\n* Segment(start, end, net, width, layer, tstamp, status)\n* Text(text, at, layer, size, thickness, bold, italic, justify, hide, tstamp)\n* Line(start, end, width, layer, tstamp, status)\n* Arc(start, end, angle, layer, width)\n* Circle(center, end, layer, width, tstamp, status)\n* Polygon(pts, layer, width, tstamp, status)\n* Curve(start, bezier1, bezier2, end, layer, width, tstamp, status)\n* Via(micro, blind, at, size, drill, layers, net, tstamp, status)\n* Layer(code, name, type, hide)\n* NetClass(name, description, clearance, trace_width, via_dia, via_drill,\n           uvia_dia, uvia_drill, diff_pair_width, diff_pair_gap, nets)\n* Zone(net, net_name, layer, tstamp, hatch_type, hatch_size, priority,\n       connect_pads, clearance, min_thickness, fill, fill_mode, arc_segments,\n       thermal_gap, thermal_bridge_width, smoothing, radius, keepout_tracks,\n       keepout_vias, keepout_copperpour, polygon, filled_polygon, fill_segments)\n* Target(shape, at, size, width, layer, tstamp)\n* Dimension(value, width, layer, text, feature1, feature2, crossbar, arrow1a,\n            arrow1b, arrow2a, arrow2b, tstamp)\n* Setup(user_trace_width, trace_clearance, zone_clearance, zone_45_only,\n        trace_min, segment_width, edge_width, via_size, uvia_size,\n        uvia_drill, uvias_allowed, blind_buried_vias_allowed, uvia_min_size,\n        uvai_min_drill, pcb_text_width, pcb_text_size, mod_edge_width,\n        mod_text_size, mod_text_width, pad_size, pad_drill, pad_to_mask_clearance,\n        solder_mask_min_width, pad_to_paste_clearance, solder_to_paste_clearance_ratio,\n        grid_origin, visible_elements, pcbplotparams)\n\n### Functions\n* find_library(library)\n* find_module(library, module)\n* list_libraries()\n* list_modules(library)\n* list_all_modules()\n* filter_by_regex()\n* flip_layer()\n\n### Global variables\n* MODULE_SEARCH_PATH\n\n# Project using pykicad\n* [pycircuit] (https://github.com/dvc94ch/pycircuit)\n\n# License\nISC License\n\nCopyright (c) 2017, David Craven\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH\nREGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY\nAND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,\nINDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM\nLOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE\nOR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR\nPERFORMANCE OF THIS SOFTWARE.",
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