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            "Natural Language :: English",
            "Programming Language :: Python :: 2.7",
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            "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)"
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        "description": "===============================\nPygMyHDL\n===============================\n\n.. image:: https://img.shields.io/pypi/v/pygmyhdl.svg\n        :target: https://pypi.python.org/pypi/pygmyhdl\n\n\nPygMyHDL is a thin wrapper around `MyHDL <myhdl.org>`_. MyHDL lets you design\nand simulate digital hardware using Python. PygMyHDL does the same thing,\nbut tries to make it a little simpler. Think of it as \"MyHDL on training wheels\".\nOnce you get enough experience with PygMyHDL, you'll probably cast it aside\nand just use straight MyHDL. That's OK; that's why I invented it.\n\n\nFeatures\n--------\n\nPygMyHDL adds the following features to MyHDL:\n\n* ``Wire`` and ``Bus`` classes for declaring single-bit and multi-bit digital signals.\n\n* ``Bus`` objects have ``.o`` and ``.i`` properties that are used to get the value on a\n  bus (that's the ``.o`` property) and to drive values onto a bus (using the ``.i`` property).\n\n* ``State`` objects are used to declare state variables for finite-state machines.\n  Each ``State`` object also stores all the defined states in its ``s`` attribute\n  for use in making comparisons to states or updating state values.\n\n* The ``@chunk`` decorator is used to indicate a function will create one or more\n  pieces of logic circuitry. These pieces will be implicitly gathered into a\n  list of logic instances that can be simulated and synthesized later.\n  (MyHDL requires you to explicitly store logic instances into Python variables\n  so they can be found and processed later.)\n\n* The decorators ``@comb_logic`` and ``@seq_logic`` are used to declare functions that\n  perform combinational and sequential logic operations, respectively. (These\n  are almost identical to MyHDL's ``@always_comb`` and ``@always_seq`` decorators\n  except they assist with the implicit instantiation of logic.)\n\n* Helper functions are provided for testing a digital design using random test\n  vectors, exhaustive test vectors, user-defined test vectors, or a simple clock signal.\n\n* The `myhdlpeek module <xesscorp.github.io/myhdlpeek>`_ is used to display the\n  results of logic simulations as waveforms or tables.\n\n\nGetting Started\n------------------\n\nBelow are some examples of Jupyter notebooks using PygMyHDL.\nUnfortunately, the Github Notebook viewer doesn't render the waveform displays\nso you'll have to download and run the notebooks locally or click on the static HTML\nlink to see what PygMyHDL can do.\n\n* The Fastest, Easiest FPGA Blinker, Ever!:\n  `[Notebook1] <https://github.com/xesscorp/pygmyhdl/blob/master/examples/1_blinker/fastest_easiest_FPGA_blinker_ever.ipynb>`_ \n  `[HTML1] <http://www.xess.com/static/media/pages/pygmyhdl/examples/1_blinker/fastest_easiest_FPGA_blinker_ever.html>`_\n\n* Hierarchy and Abstraction and Ursidae, Oh My!:\n  `[Notebook2] <https://github.com/xesscorp/pygmyhdl/blob/master/examples/2_hierarchy/hierarchy_and_abstraction_and_ursidae_oh_my.ipynb>`_\n  `[HTML2] <http://www.xess.com/static/media/pages/pygmyhdl/examples/2_hierarchy/hierarchy_and_abstraction_and_ursidae_oh_my.html>`_\n\n* Pulse Width Modulators:\n  `[Notebook3] <https://github.com/xesscorp/pygmyhdl/blob/master/examples/3_pwm/pwm.ipynb>`_ \n  `[HTML3] <http://www.xess.com/static/media/pages/pygmyhdl/examples/3_pwm/pwm.html>`_\n\n* Block (RAM) Party!:\n  `[Notebook4] <https://github.com/xesscorp/pygmyhdl/blob/master/examples/4_blockram/block_ram_party.ipynb>`_ \n  `[HTML4] <http://www.xess.com/static/media/pages/pygmyhdl/examples/4_blockram/block_ram_party.html>`_\n\n* FSMs Without Monsters!:\n  `[Notebook5] <https://github.com/xesscorp/pygmyhdl/blob/master/examples/5_fsm/fsm.ipynb>`_ \n  `[HTML5] <http://www.xess.com/static/media/pages/pygmyhdl/examples/5_fsm/fsm.html>`_\n\n|\n\n* Free software: MIT license\n\n\n\n\nHistory\n-------\n\n\n0.0.3 (2017-11-05)\n___________________________\n\n* Added State object for working with finite-state machines in PygMyHDL.\n\n\n0.0.2 (2017-09-20)\n___________________________\n\n* Fixed Bus object so my_bus.o[m:n] now calls my_bus(m, n) to get a shadow slice instead of creating an array of wires.\n\n\n0.0.1 (2017-08-30)\n___________________________\n\n* First release on PyPI.\n",
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