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        "author": "Shinya Takamaeda-Yamazaki",
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        "description": "PyCoRAM\n=======\n\nPython-based Portable IP-core Synthesis Framework for FPGA-based\nComputing\n\nCopyright (C) 2013, Shinya Takamaeda-Yamazaki\n\nE-mail: shinya\\_at\\_is.naist.jp\n\nLicense\n=======\n\nApache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)\n\nPublication\n===========\n\nIf you use PyCoRAM in your research, please cite our paper.\n\n-  Shinya Takamaeda-Yamazaki, Kenji Kise and James C. Hoe: PyCoRAM: Yet\n   Another Implementation of CoRAM Memory Architecture for Modern\n   FPGA-based Computing, The Third Workshop on the Intersections of\n   Computer Architecture and Reconfigurable Logic (CARL 2013)\n   (Co-located with MICRO-46), December 2013.\n   `Paper <http://users.ece.cmu.edu/~jhoe/distribution/2013/carl13pycoram.pdf>`__\n   `Slide <http://www.slideshare.net/shtaxxx/pycoramcarl2013>`__\n\n::\n\n    @inproceedings{Takamaeda:2013:CARL:PyCoRAM,\n    author = {Takamaeda-Yamazaki, Shinya and Kise, Kenji and Hoe, James C.},\n    title = {{PyCoRAM: Yet Another Implementation of CoRAM Memory Architecture for Modern FPGA-based Computing}},\n    booktitle={Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013)},\n    month={Dec},\n    year = {2013},\n    location = {Davis, CA},\n    } \n\n-  Zynq + PyCoRAM (+ Debian) (slideshare, in Japanese)\n   `Slide <http://www.slideshare.net/shtaxxx/zynqpycoram>`__\n\n-  PyCoRAM for HLS meet up (slideshare, in Japanese)\n   `Slide <http://www.slideshare.net/shtaxxx/pycoram20150116hls>`__\n\nWhat's PyCoRAM?\n===============\n\nPyCoRAM is a Python-based portable IP-core synthesis framework with\nCoRAM (Connected RAM) memory architecture.\n\nPyCoRAM framework generates a portable IP-core package from computing\nlogic descriptions in Verilog HDL and memory access pattern descriptions\nin Python. Designers can easily build an FPGA-based custom accelerator\nusing a generated IP-core with any common IP-cores on vendor-provided\nEDA tools. PyCoRAM framework includes (1) the Verilog-to-Verilog design\ntranslation compiler and (2) the Python-to-Verilog high-level synthesis\n(HLS) compiler for generating control circuits of memory operations.\n\nThere are some major differences between PyCoRAM and the original\nsoft-logic implementation of CoRAM.\n\n-  Memory access pattern representation in Python\n\n   -  The original CoRAM uses C language to represent a memory access\n      pattern (called 'control thread').\n   -  In PyCoRAM, you can easily describe them by using popular\n      lightweight scripting language.\n   -  A Python script of memory access patterns is translated into an\n      RT-level hardware design in Verilog HDL by the Python-to-Verilog\n      high-level synthesis compiler.\n\n-  Commercial interconnect supports (AMBA AXI4 and Altera Avalon)\n\n   -  The original CoRAM uses CONNECT to generate an on-chip\n      interconnect.\n   -  PyCoRAM compiler generates a IP-core design with AMBA AXI4 or\n      Altera Avalon. Both are commonly used on vendor-provided EDA\n      tools.\n\n-  Parameterized RTL Design Support\n\n   -  The original CoRAM has some limitations in Verilog HDL description\n      of computing logic, such as no supports of generate statement.\n   -  PyCoRAM has a sophisticated RTL analyzer/translator to convert RTL\n      descriptions into synthesizable IP-core package under memory\n      abstractions of CoRAM.\n\nInstallation\n============\n\nRequirements\n------------\n\n-  Python: 2.7, 3.4 or later\n\nPython3 is recommended.\n\n-  Icarus Verilog: 0.9.7 or later\n\nInstall on your platform. For exmple, on Ubuntu:\n\n::\n\n    sudo apt-get install iverilog\n\n-  Jinja2: 2.8 or later\n-  pytest: 2.8.2 or later\n-  pytest-pythonpath: 0.7 or later\n\nInstall on your python environment by using pip.\n\n::\n\n    pip install jinja2 pytest pytest-pythonpath\n\n-  Pyverilog: 1.0.0 or later\n\nInstall from pip:\n\n::\n\n    pip install pyverilog\n\nInstall\n-------\n\nInstall PyCoRAM.\n\n::\n\n    python setup.py install\n\nOn Docker\n---------\n\nDockerfile is available, so that you can try PyCoRAM on Docker without\nany installation on your host platform.\n\n::\n\n    cd docker\n    sudo docker build -t user/pycoram .\n    sudo docker run --name pycoram -i -t user/pycoram /bin/bash\n    cd PyCoRAM/tests/single_memory/\n    make build\n    make sim\n\nGetting Started\n===============\n\nYou can use the pycoram command from your console.\n\n::\n\n    pycoram\n\nYou can find some examples in 'PyCoRAM/examples/' and 'PyCoRAM/tests'.\n\nLet's begin PyCoRAM by an example in 'tests/single\\_memory'. You will\nfind two source files.\n\n-  ctrl\\_thread.py : Control-thread definition in Python\n-  userlogic.v : User-defined Verilog code using CoRAM memory blocks\n\nType 'make' to build a PyCoRAM IP-core from the source files. Then type\n'make run' to simulate sample system.\n\n::\n\n    make build\n    make sim\n\nInstead, you can type commands as below directly at 'PyCoRAM' directory.\n\n::\n\n    pycoram default.config -t userlogic -I include tests/single_memory/ctrl_thread.py tests/single_memory/userlogic.v\n    iverilog -I pycoram_userlogic_v1_00_a/hdl/verilog/ pycoram_userlogic_v1_00_a/test/test_pycoram_userlogic.v \n    ./a.out\n\nPyCoRAM compiler generates a directory for IP-core\n(pycoram\\_userlogic\\_v1\\_00\\_a, in this example).\n\n'pycoram\\_userlogic\\_v1\\_00\\_a.v' includes - IP-core RTL design\n(hdl/verilog/pycoram\\_userlogic.v) - Test bench\n(test/test\\_pycoram\\_userlogic.v) - XPS setting files\n(pycoram\\_userlogic\\_v2\\_1\\_0.{mpd,pao,tcl}) - IP-XACT file\n(component.xml)\n\nA bit-stream can be synthesized by using Xilinx Platform Studio, Xilinx\nVivado, and Altera Qsys. In case of XPS, please copy the generated\nIP-core into 'pcores' directory of XPS project.\n\nThis project has some examples in 'PyCoRAM/examples/' and\n'PyCoRAM/tests'. To build them, please modify 'Makefile', so that the\ncorresponding files and parameters are selected (especially INPUT,\nMEMIMG and USERTEST).\n\nPyCoRAM Command Options\n=======================\n\nCommand\n-------\n\n::\n\n    pycoram [config] [-t topmodule] [-I includepath]+ [--memimg=filename] [--usertest=filename] [file]+\n\nDescription\n-----------\n\n-  file\n\n   -  User-logic Verilog file (.v) and control-thread definition file\n      (.py). Automatically, .v file is recognized as a user-logic\n      Verilog file, and .py file recongnized as a control-thread\n      definition, respectively.\n\n-  config\n\n   -  Configuration file which includes memory and device specification\n\n-  -t\n\n   -  Name of user-defined top module, default is \"userlogic\".\n\n-  -I\n\n   -  Include path for input Verilog HDL files.\n\n-  --memimg\n\n   -  DRAM image file in HEX DRAM (option, if you need). The file is\n      copied into test directory. If no file is assigned, the array is\n      initialized with incremental values.\n\n-  --usertest\n\n   -  User-defined test code file (option, if you need). The code is\n      copied into testbench script.\n\nRelated Project\n===============\n\n`Pyverilog <https://github.com/PyHDI/Pyverilog>`__ - Python-based\nHardware Design Processing Toolkit for Verilog HDL - Used as basic code\nanalyser and generator in PyCoRAM\n\n`CoRAM <http://www.ece.cmu.edu/coram/doku.php?id=home>`__ - A General\nPurpose Memory Architecture for FPGAs - The original CoRAM developed at\nCMU",
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