{ "info": { "author": "Julian Hammer", "author_email": "julian.hammer@fau.de", "bugtrack_url": null, "classifiers": [ "Development Status :: 4 - Beta", "Intended Audience :: Developers", "Intended Audience :: Science/Research", "License :: OSI Approved :: GNU Affero General Public License v3", "Programming Language :: Python :: 2", "Programming Language :: Python :: 2.7", "Programming Language :: Python :: 3", "Programming Language :: Python :: 3.4", "Topic :: Scientific/Engineering", "Topic :: Software Development", "Topic :: Utilities" ], "description": "pycachesim\n==========\n\nA single-core cache hierarchy simulator written in python.\n\n.. image:: https://travis-ci.org/RRZE-HPC/pycachesim.svg?branch=master\n :target: https://travis-ci.org/RRZE-HPC/pycachesim?branch=master\n\nThe goal is to accurately simulate the caching (allocation/hit/miss/replace/evict) behavior of all cache levels found in modern processors. It is developed as a backend to `kerncraft `_, but is also planned to introduce a command line interface to replay LOAD/STORE instructions.\n\nCurrently supported features:\n * Inclusive cache hierarchies\n * LRU, MRU, RR and FIFO policies \n * N-way cache associativity\n * Write-allocate with write-back caches\n * Non-write-allocate with write-through caches\n * Write-combining with sub-blocking\n * Tracking of cacheline states (e.g., using dirty bits)\n * Speed (core is implemented in C)\n * Python 2.7+ and 3.4+ support, with no other dependencies\n\nPlanned features:\n * Report cachelines on all levels (preliminary support through ``backend.verbosity > 0``)\n * Report timeline of cache events (preliminary support through ``backend.verbosity > 0``)\n * Visualize events (html file?)\n * Interface to Valgrind Infrastructure (see `Lackey `_) for access history replay.\n * (uncertain) instruction cache\n * Optional classification into compulsory/capacity and conflict misses (by simulating other cache configurations in parallel)\n * (uncertain) multi-core support\n \nLicense\n-------\n\npycachesim is licensed under AGPLv3.\n\nUsage\n-----\n\n.. code-block:: python\n\n from cachesim import CacheSimulator, Cache, MainMemory\n \n mem = MainMemory()\n l3 = Cache(\"L3\", 20480, 16, 64, \"LRU\") # 20MB: 20480 sets, 16-ways with cacheline size of 64 bytes\n mem.load_to(l3)\n mem.store_from(l3)\n l2 = Cache(\"L2\", 512, 8, 64, \"LRU\", store_to=l3, load_from=l3) # 256KB\n l1 = Cache(\"L1\", 64, 8, 64, \"LRU\", store_to=l2, load_from=l2) # 32KB\n cs = CacheSimulator(l1, mem)\n \n cs.load(2342) # Loads one byte from address 2342, should be a miss in all cache-levels\n cs.store(512, length=8) # Stores 8 bytes to addresses 512-519,\n # will also be a load miss (due to write-allocate)\n cs.load(512, length=8) # Loads from address 512 until (exclusive) 520 (eight bytes)\n \n cs.force_write_back()\n cs.print_stats()\n \nThis should return:\n\n.. code-block:: python\n\n CACHE *******HIT******** *******MISS******* *******LOAD******* ******STORE*******\n L1 1 ( 8B) 2 ( 65B) 3 ( 73B) 1 ( 8B)\n L2 0 ( 0B) 2 ( 128B) 2 ( 128B) 1 ( 64B)\n L3 0 ( 0B) 2 ( 128B) 2 ( 128B) 1 ( 64B)\n MEM 2 ( 128B) 0 ( 0B) 2 ( 128B) 1 ( 64B)\n\nEach row refers to one memory-level, starting with L1 and ending with main memory. The 3 loads in L1 are the sum of all individual accesses to the cache-hierarchy. 1 (from first load) + 1 (from store with write-allocate) + 1 (from second load) = 3.\n\nThe 1 hit, is for bytes which were cached already. Internally the pycachesim operates on cache-lines, which all addresses get transformed to. Thus, the two misses throughout all cache-levels are actually two complete cache-lines and after the cache-line had been loaded the consecutive access to the same cache-line are handled as hits. That is also the reason why data sizes increase from L1 to L2. L1 is accessed byte-wise and L2 only with cache-line granularity.\n\nSo: hits, misses, stores and loads in L1 are byte-wise. Every other statistical information are based on cache-lines.\n\nWhen using victim caches, setting `victims_to` to the victim cache level, will cause pycachesim to forward unmodified cache-lines to this level on replacement. During a miss, victims_to is checked for availability and only hit if it the cache-line is found. This means, that load stats will equal hit stats in victim caches and misses should always be zero.\n\nComparison to other Cache Simulators\n====================================\n\nWhile searching for more versatile cache simulator for kerncraft, I stumbled across the following:\n\n * gem5_:\n Very fully-featured full system simulator. Complex to extract only the memory subsystem\n * dineroIV_:\n Nice and simple code, but does not support exclusive caches and not available under open source license.\n * cachegrind_:\n Maintained and stable code of a well established open source project, but only supports inclusive first and last level caches.\n * callgrind_:\n see cachegrind\n * SMPcache_:\n Only supports one single cache and runs on Windows with GUI. Also not freely available.\n * CMPsim_:\n Was only academically published and source code never made available.\n * CASPER_:\n Was only academically published and source code never made available.\n\n=========== ================= =========== =============== ================= ======== ======== ========= ======= ======== ============== ============== =========== =============== ================= ===================================\nPackage instructions [0]_ blocks [1]_ sub-blocks [2]_ associtivity [3]_ LRU [4]_ MRU [4]_ FIFO [4]_ RR [4]_ CCC [5]_ 3+ levels [6]_ exclusive [7]_ victim [8]_ multi-core [9]_ API [10]_ open source [11]_\n=========== ================= =========== =============== ================= ======== ======== ========= ======= ======== ============== ============== =========== =============== ================= ===================================\ngem5_ x x ? x x x x ? ? x ? ? ? python, ruby, c++ yes, BSD-style \ndineroIV_ x x x x x x x x x c no, free for non-comercial use \ncachegrind_ x x x x cli yes, GPLv2 \ncallgrind_ x x x x cli yes, GPLv2 \nSMPcache_ x x x x x ? Windows GUI no, free for education und research \nCMPsim_ x x x x x x x ? ? x ? no, source not public \nCASPER_ x x x x x x x x x x x perl, c no, source not public \npycachesim x x x x x x x x x x python, C backend yes, AGPLv3 \n=========== ================= =========== =============== ================= ======== ======== ========= ======= ======== ============== ============== =========== =============== ================= ===================================\n\n.. _gem5: http://gem5.org/Main_Page\n.. _dineroIV: http://pages.cs.wisc.edu/~markhill/DineroIV/\n.. _cachegrind: http://valgrind.org/docs/manual/cg-manual.html\n.. _callgrind: http://valgrind.org/docs/manual/cl-manual.html\n.. _SMPcache: http://arco.unex.es/smpcache/\n.. _CMPsim: http://eng.umd.edu/~blj/papers/mobs2008.pdf\n.. _CASPER: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1240655\n\n.. [0] Instruction cache support (typically L1I)\n.. [1] Cacheline/block granular caching\n.. [2] Sub-blocking/sectoring for in cache-storage\n.. [3] Support for n-way associativity\n.. [4] Support least-recently-used (LRU), most-recently-used (MRU), first-in-last-out (FIFO), random (RR) replacement policy\n.. [5] Classification of misses into: compulsory (first time access), capacity (access after replacement), conflict (would have been a hit with full-associativity)\n.. [6] Combining of at least three cache levels\n.. [7] Exclusive cache relations (two levels may not share the same cacheline)\n.. [8] Victim caches, where only evicted lines endup(e.g., AMD Bulldozer L3)\n.. [9] Multi-core cache hierarchies with private and shared caches and cache coherency protocol\n.. [10] Supported interfaces (cli = command-line-interface)\n.. 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