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        "author": "Google LLC",
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        "classifiers": [
            "Intended Audience :: Developers",
            "License :: OSI Approved :: Apache Software License",
            "Operating System :: OS Independent",
            "Programming Language :: Python :: 3",
            "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
            "Topic :: System :: Hardware"
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        "description": "# PCB Design Language\nA programming way to design schematics.\n\n## Installing\n\n[![PyPI version](https://badge.fury.io/py/pcbdl.svg)](https://pypi.org/project/pcbdl/)\n\n\tsudo apt-get install python3 python3-pip python3-pygments\n\n\tsudo pip3 install pcbdl\n\n## Interactive terminal\n\nA good way to try various features without having to write a file separately.\n\n\tpython3 -i -c \"from pcbdl import *\"\n\n## Language\n\nPCBDL's goal is to allow designing schematics via Code. Similar to how VHDL or Verilog are ways to represent Logic Diagrams in code form, PCBDL the analogous of that but for EDA schematics.\n\nTo start one should define a couple of nets:\n\n\t>>> vcc, gnd = Net(\"vcc\"), Net(\"gnd\")\n\t>>> vin = Net(\"vin\")\n\t>>> base = Net(\"base\")\n\nWe then can connect various components between those nets with the `<<` operator and the `to=` argument (for the other side):\n\n\t>>> base << C(\"1000u\", to=vin)\n\t>>> base << (\n\t\tR(\"1k\", to=vcc),\n\t\tR(\"1k\", to=gnd),\n\t)\n\n2 pin devices (aka JellyBean in pcbdl) like capacitors and resistors are one of the easiest things to connect. Internally they have a primary (connected with `>>`) and secondary, other side, pin (connected with `to=`).\n\nLet's try to get more complicated by defining a transistor and connect some of its pins.\n\n\t>>> class Transistor(Part):\n\t\tREFDES_PREFIX = \"Q\"\n\t\tPINS = [\"B\", \"C\", \"E\"]\n\t...\n\t>>> q = Transistor()\n\t>>> base << q.B\n\nNets can also be created anonymously if started from a part's pins:\n\n\t>>> q.E << (\n\t\tR(\"100\", to=gnd),\n\t\tC(\"1u\", to=gnd),\n\t)\n\nLet's finish our class A amplifier (note how we created the \"vout\" net in place, and how we gave a name (\"Rc\") to one of our resistors):\n\n\t>>> q.C << (\n\t\tC(\"100u\", to=Net(\"vout\")),\n\t\tR(\"100\", \"Rc\", to=vcc),\n\t)\n\nNote: One can find a completed version of this amplifier in `examples/class_a.py`:\n\n\tpython3 -i examples/class_a.py\n\n\nOne can now give automatic consecutive reference designators to components that haven't been named manually already:\n\n\t>>> global_context.autoname()\n\nThen one can explore the circuit:\n\n\t>>> global_context.parts_list\n\t[R1, R2, R3, Rc, C10, C11, Q1, C12]\n\n\t>>> global_context.parts_list[0].refdes\n\t'R1'\n\t>>> global_context.parts_list[0].value\n\t'1k\u03a9'\n\t>>> global_context.parts_list[0].pins\n\t(R1.P1, R1.P2)\n\t>>> global_context.parts_list[0].pins[1].net\n\tVCC(connected to R1.P2, R2.P2)\n\n\t>>> nets\n\tOrderedDict([('VCC', VCC(connected to R1.P2, R2.P2)), ('GND', GND(connected to R3.P2, Rc.P2, C10.-)), ('VIN', VIN(connected to C11.-)), ('VOUT', VOUT(connected to C12.-))])\n\n\t>>> nets[\"GND\"]\n\tGND(connected to R3.P2, Rc.P2, C10.-)\n\n## Examples\n\nFound in the `examples/` folder. Another way to make sure the environment is sane.\nOne can just \"run\" any example schematic with python, add -i to do more analysis operations on the schematic.\n\n* `voltage_divider.py`: Very simple voltage divider\n* `class_a.py`: Class A transistor amplifier, a good example to how a complicatedish analog circuit would look like.\n* `servo_micro.py`: **Servo micro schematics**, reimplementation in pcbdl, [originally an 8 page pdf schematic](https://www.chromium.org/chromium-os/servo/servomicro).\n\n## Exporting\n\n### Netlists\n\nThe main goal of this language is to aid in creating PCBs. The intermediate file format that layout programs (where one designs physical boards) is called a netlist. We must support outputting to that (or several of such formats).\n\nFor now we have a **minimum viable example** of an exporter for the Allegro Cadence netlists (found in `netlist.py`):\n\n\t>>> generate_netlist(\"/tmp/some_export_location\")\n\n### HTML\n\nThis produces a standalone html page with everything cross-linked:\n\n* List of nets with links to the parts and pins on each\n* List of parts with the part properties and a list of pins linking to the nets connected\n* Highlighted source code, with every variable and object linked to the previous 2 lists\n\nHere's an example of such a [html output for servo micro](https://google.github.io/pcbdl/examples/servo_micro.html).\n\n### Schematics / Graphical representation of the circuit\n\nIn order for schematics to be more easily parsable, we want to graphically display them. The [netlistsvg](https://github.com/nturley/netlistsvg) project has been proven to be an excellent tool to solve the hard problems of this. See `pcbdl/netlistsvg.py` for the implementation.\n\n1. Convert a pcbdl schematic back into a traditional schematic\n\n\t`generate_svg('svg_filename')`\n\n\tHere's the [svg output for the servo_micro example](https://google.github.io/pcbdl/examples/servo_micro.svg).\n\n2. Isolated schematics for how a particular thing is hooked up:\n\t* I2C map, ([servo_micro's](https://google.github.io/pcbdl/examples/servo_micro.i2c.svg))\n\n\t`generate_svg('svg_filename', net_regex='.*(SDA|SCL).*', airwires=0)`\n\n\t* Power connections ([servo_micro's](https://google.github.io/pcbdl/examples/servo_micro.power.svg))\n\n\t`generate_svg('svg_filename', net_regex='.*(PP|GND|VIN|VBUS).*')`\n\n3. Block diagrams of the overall system\n\t* This depends on how the schematics is declared, if it's not hierarchical enough, it won't have many \"blocks\" to display\n\t* This task is dependent on allowing hierarchies in pcbdl\n\n### BOM\n\nBill of Materials would be a trivial thing to implement in pcbdl.\n\n## ERC\n\nElectrical Rule Checking. How to unit test a schematic?\n\nThis is a big **TODO** item. The basic idea is that the pins will get annotated more heavily than normal EDA software.\n\nPins will have beyond just simple input/output/open drain/power properties, but will go into detail with things like:\n* Power well for both inputs and outputs\n* ViH, ViL\n* Output voltages\n\nWith this information it should be possible to make isolated spice circuits to check for current leaks.\nFor every net, for every combination of output pins on that net, are all the input pins receiving proper voltages?\n\n## Importing from traditional EDA schematics\n\nGiven that graphical exporting might be impossible, and in lieu of the language being slightly more unreadable than normal schematics, perhaps we should just use pcbdl as an intermediate data format or a library.\n\nThe way one would use it would be to import a kicad schematic, annotate it with a few more classes (for BOM and ERC purposes, unless we can find a way to put all metadata in the kicad schematics). Then all exporting and analysis features of pcbdl can still be used.\n\nA kicad importer should be pretty trivial to implement. **TODO**\n\n## Support\n\nThis is not an officially supported Google product.\n\nThe language itself is still in flux, things might change. A lot of the syntax was added as a demo of what could be possible, might still need polishing. Please don't use this language without expecting some tinkering to keep your schematics up to date to the language.\n\n## Credits / Thanks\n\n* [CBOLD](http://cbold.com/) for the idea\n* [netlistsvg](https://github.com/nturley/netlistsvg) for svg output support\n* Chrome OS Hardware Design Team for feedback\n\n\n",
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