{ "info": { "author": "T. Kramer", "author_email": "dont@spam.me", "bugtrack_url": null, "classifiers": [ "Development Status :: 3 - Alpha", "License :: OSI Approved :: GNU Affero General Public License v3 or later (AGPLv3+)", "Programming Language :: Python :: 3", "Topic :: Scientific/Engineering", "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)" ], "description": "# LibreCell - Lib\nCharacterization kit for CMOS cells.\n\n## Getting started\n\nSee install instructions in top-project.\n\n### Characterize a cell\nThe following example determines the input capacitances and timing delays of a combinational cell.\n\nIt is assumed that `FreePDK45` is installed in the users home directory.\n\nRequired inputs are:\n* --liberty: A template liberty file which defines how the cells should be characterized.\n* --include: SPICE files or models to be included.\n* --spice: A SPICE file which contains the transistor level circuit of the cell (best including extracted parasitic capacitances).\n* --cell: Name of the cell to be characterized.\n* --output: Output liberty file which will contain the characterization data.\n\n```sh\nlclayout --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \\\n\t--include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \\\n\t--spice ~/FreePDK45/osu_soc/lib/source/netlists/AND2X1.pex.netlist \\\n\t--cell AND2X1 \\\n\t--output /tmp/and2x1.lib\n```\n\n\n", "description_content_type": "text/markdown", "docs_url": null, "download_url": "", "downloads": { "last_day": -1, "last_month": -1, "last_week": -1 }, "home_page": "https://codeberg.org/tok/librecell", "keywords": "cmos cell characterization vlsi asic", "license": "AGPL", "maintainer": "", "maintainer_email": "", "name": "librecell-lib", "package_url": "https://pypi.org/project/librecell-lib/", "platform": "", "project_url": "https://pypi.org/project/librecell-lib/", "project_urls": { "Homepage": "https://codeberg.org/tok/librecell" }, "release_url": "https://pypi.org/project/librecell-lib/0.0.3.post0/", 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