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        "author": "T. Kramer",
        "author_email": "dont@spam.me",
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            "Development Status :: 3 - Alpha",
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        "description": "# LibreCell - Layout\nCMOS Standard Cell layout generator.\n\n## Getting started\n\nSee install instructions in top-project.\n\n### Generate a layout\nGenerate a layout from a SPICE netlist which includes the transistor sizes:\n* --output-dir: Directory which will be used to store GDS and LEF of the cell\n* --tech: Python script file containing design rules and technology related data\n* --netlist: A SPICE netlist containing the netlist of the cell as a sub circuit (`.subckt`).\n* --cell: Name of the cell. Must match the name of the sub circuit in the SPICE netlist.\n\n```sh\nmkdir mylibrary\nlclayout --output-dir mylibrary --tech examples/dummy_tech.py --netlist examples/cells.sp --cell AND2X1\n```\n\n## Adapting design rules\nDesign rulesi and technology related data need to be encoded in a Python script file as shown in `examples/dummy_tech.py`.\n\n\n",
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        "license": "OHL-S v2.0",
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        "name": "librecell-layout",
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