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        "author": "Keyi Zhang",
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        "description": "Kratos\n======\n\n|Build Status| |Appveyor Build status| |PyPI - Version|\n|Coverage| |Documentation Status|\n\nKratos is a hardware design language written in C++/Python. It\ndifferentiates itself from other DSL with the following design\nphilosophy:\n\n- Fully debuggable: debug hardware just like debugging Python code!\n  Thanks to `hgdb`_.\n- Highly efficient: Python frontend powered by\n  Modern C++ binding. Designed with multi-processing in mind.\n- Human-readable verilog: we know how difficult it is to read machine\n  generated verilog. kratos has multiple passes to produce nice-looking\n  verilog.\n- Generator of generators: every python object is a generator\n  that can be modified at any time, even after instantiation. This allows\n  complex passes on the generators without ripping old structure apart.\n- Keep the good parts of SystemVerilog, such as ``always_ff``,\n  ``always_comb``, ``interface``, and ``unique case``. Users control\n  how and when to generate these semantics.\n- Single source of truth: kratos encourages users to infuse generator\n  information inside generator itself. This makes debugging and\n  verification much easier.\n- Static elaboration: kratos allows user to write parametrized code,\n  even in the ``always`` block, all in Python.\n- Type checking: kratos check the variable types\n  for each assignment to make sure there is no implicit conversion.\n\nInstall\n-------\n\n::\n\n   pip install kratos\n\nPre-built wheels support all Python 3.6+ on Linux, Windows, and\nOSX. To build it from scratch, you need a ``C++17`` compatible\ncompiler, such as ``g++-8`` or ``clang-8``.\n\nDocumentation and Examples\n--------------------------\n\nYou can check the documentation at `Read the\nDocs <https://kratos-doc.readthedocs.io/en/latest/>`__.\n\nHere are some examples to showcase the ability of kratos.\n\nAsync Reset Register\n~~~~~~~~~~~~~~~~~~~~\n\nPython code that parametrizes based on the ``width``. Notice that we\nspecify the sensitivity of the ``always_ff`` block when defining\n``seq_code_block``.\n\n.. code:: python\n\n   class AsyncReg(Generator):\n       def __init__(self, width):\n           super().__init__(\"register\")\n\n           # define inputs and outputs\n           self._in = self.input(\"in\", width)\n           self._out = self.output(\"out\", width)\n           self._clk = self.clock(\"clk\")\n           self._rst = self.reset(\"rst\")\n\n           # add combination and sequential blocks\n           self.add_code(self.seq_code_block)\n\n       @always_ff((posedge, \"clk\"), (posedge, \"rst\"))\n       def seq_code_block(self):\n           if self._rst:\n               self._out = 0\n           else:\n               self._out = self._in\n\nHere is the generated SystemVerilog\n\n.. code:: SystemVerilog\n\n   module register (\n     input logic clk,\n     input logic [15:0] in,\n     output logic [15:0] out,\n     input logic rst\n   );\n\n\n   always_ff @(posedge clk, posedge rst) begin\n     if (rst) begin\n       out <= 16'h0;\n     end\n     else out <= in;\n   end\n   endmodule   // register\n\n\nFanout module\n~~~~~~~~~~~~~\n\nThis is another example to showcase the kratos' ability to produce high-quality\nSystemVerilog. In practice we would not write it this way.\n\n.. code:: python\n\n   class PassThrough(Generator):\n       def __init__(self, num_loop):\n           super().__init__(\"PassThrough\")\n           self.in_ = self.input(\"in\", 1)\n           self.out_ = self.output(\"out\", num_loop)\n           self.num_loop = num_loop\n\n           self.add_code(self.code)\n\n       @always_comb\n       def code(self):\n           if self.in_:\n               for i in range(self.num_loop):\n                   self.out_[i] = 1\n           else:\n               for i in range(self.num_loop):\n                   self.out_[i] = 0\n\nHere is generated SystemVerilog. Notice that the iteration variable ``i``\nhas been properly checked and resized to avoid index out of range.\n\n.. code:: SystemVerilog\n\n  module PassThrough (\n    input logic in,\n    output logic [3:0] out\n  );\n\n  always_comb begin\n    if (in) begin\n      for (int unsigned i = 0; i < 4; i += 1) begin\n          out[2'(i)] = 1'h1;\n        end\n    end\n    else begin\n      for (int unsigned i = 0; i < 4; i += 1) begin\n          out[2'(i)] = 1'h0;\n        end\n    end\n  end\n  endmodule   // PassThrough\n\n\nHow to debug\n------------\n\nBecause Python is quite slow, By default the debug option is off. You\ncan turn on debugging for individual modules. See\n``tests/test_generator.py`` for more details).\n\n\nUse an IDE Debugger\n-------------------\n\n.. image:: https://cdn.jsdelivr.net/gh/Kuree/kratos-vscode@master/images/demo.gif\n     :alt: demo\n\nThanks to the native support of `hgdb`_, you can debug the generated RTL with a\nprofessional debugger as if you are debugging Python code. ``gdb``-like console version\nis also available. Check out `hgdb`_ to see how it works!\n\n\n\n.. |Build Status| image:: https://github.com/Kuree/kratos/workflows/Linux%20Wheel%20Test/badge.svg\n   :target: https://github.com/Kuree/kratos/actions\n.. |Appveyor Build status| image:: https://ci.appveyor.com/api/projects/status/en1u36q9tdqbaoh9/branch/master?svg=true\n   :target: https://ci.appveyor.com/project/Kuree/kratos/branch/master\n.. |PyPI - Version| image:: https://badge.fury.io/py/kratos.svg\n   :target: https://pypi.org/project/kratos/\n.. |Coverage| image:: https://codecov.io/gh/Kuree/kratos/branch/master/graph/badge.svg\n  :target: https://codecov.io/gh/Kuree/kratos\n.. |Documentation Status| image:: https://readthedocs.org/projects/kratos-doc/badge/?version=latest\n   :target: https://kratos-doc.readthedocs.io/en/latest/?badge=latest\n.. _hgdb: https://github.com/Kuree/hgdb\n\n\n",
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