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    "info": {
        "author": "Jonathan Tremesaygues",
        "author_email": "jonathan.tremesaygues@slaanesh.org",
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        "classifiers": [
            "License :: CeCILL-B Free Software License Agreement (CECILL-B)",
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            "Programming Language :: Python :: 3"
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        "description": "# kFPGA\n[![Build Status](https://jenkins.slaanesh.org/job/kfpga/badge/icon)](https://jenkins.slaanesh.org/job/kfpga/)\n\nkFPGA is an opensource platform for creating and programming FPGA cores.\n\n## Installation\n### Using pip\n```\npython3 -m pip install kfpga\n```\n### From source\n```\ngit clone https://git.slaanesh.org/killruana/kfpga.git\npython3 kfpga/setup.py install\n```\n\n\n## Usage\n### Creating a new kFPGA core\nFirst, create the kFPGA core\n```\nkfpga-creator createcore \\\n    --width 5 \\\n    --height 5 \\\n    --io 4 \\\n    --clocks 1 \\\n    --sets 1 \\\n    --resets 1 \\\n    --enables 1 \\\n    --interconnect_width 10 \\\n    --le 4 \\\n    --lut 4 \\\n    kFPGADemoCore \n```\n\nThen, you can generate the RTL of the core like this\n```\nkfpga-creator generatertl \\\n    kFPGADemoCore/kFPGADemoCore.kcp\n```\n\n### Implementation\nkFPGA cores can be implemented on FPGA for testing purpose, as an ASIC or integrated in a SoC.\n\nTODO\n\n### Programming\nkFPGA cores are programmed with the `kfpga-programmer` command\n\nTODO\n\n## Architecture\nCurrently, the architecture of kFPGA core is very simple: only LUTs and interconnect. The following functionalities are planned:\n* DSP\u00a0blocks\n* memory blocks\n* carry chain\n* support for generated clock, set, reset and enable signals\n\n",
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        "keywords": "kfpga fpga",
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        "name": "kfpga",
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        "summary": "An open source FPGA",
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