{ "info": { "author": "oddball", "author_email": "", "bugtrack_url": null, "classifiers": [ "Development Status :: 4 - Beta", "License :: OSI Approved :: GNU General Public License v2 (GPLv2)", "Programming Language :: Python :: 2.7", "Programming Language :: Python :: 3.6", "Topic :: Text Processing :: Linguistic" ], "description": "ipxact2systemverilog ipxact2rst ipxact2vhdl\n-------------------------------------------\n\n.. image:: https://circleci.com/gh/oddball/ipxact2systemverilog.svg?style=shield&circle-token=071d263d097ebb33943a749ecb66549c9f0512ed\n :target: https://circleci.com/gh/oddball/ipxact2systemverilog\n\n\nThis software takes an IP-XACT description of register banks, and generates synthesizable VHDL and SystemVerilog packages and ReStructuredText documents. It ONLY considers register bank descriptions. The software does not generate OVM or UVM testbench packages. In the example/tb directory there is an example of how to use the generated packages. \n\nUsage\n-----\n\n::\n \n pip install ipxact2systemverilog\n\n\n::\n \n ipxact2systemverilog --srcFile FILE --destDir DIR\n ipxact2rst --srcFile FILE --destDir DIR\n ipxact2vhdl --srcFile FILE --destDir DIR\n\n\nDevelopment\n-----------\nSee https://github.com/oddball/ipxact2systemverilog\n\nTesting the example file\n========================\n::\n \n make\n\nIf Modelsim is installed:\n::\n \n make compile\n make sim\n\n\nNote\n====\nYou can use http://rst2pdf.ralsina.me to make a pdf from the generated reStructuredText.\nYou can use http://pandoc.org/demos.html to convert to almost any fileformat.\n\n\nValidation\n==========\nTo validate your xml\n::\n \n xmllint --noout --schema ipxact2systemverilog/xml/component.xsd example/input/test.xml\n\n\n\nDependencies\n============\n\n::\n \n pip install docutils lxml tabulate future\n\n\nDependencies used by makefile\n=============================\nThese are not needed for ipxact2systemverilog, but used for generating some of the files in example/output\n\n::\n \n pip2 install rst2pdf\n brew install pandoc\n\n\nWorking in development mode for pypi\n====================================\n\n::\n \n pip3 install -e .\n python3 setup.py sdist\n python3 setup.py sdist upload -r pypi\n \n\nTODO\n====\n* Should compile the verilog output with http://iverilog.icarus.com/ but sadly icarus does not support enough SV yet \n* A better testbench for the generated packages should be implemented.\n* More complicated IPXACT files should be added and tried out.\n* Add support for the SystemVerilog generator to have a register field of an enumerated type.\n* Use http://pyxb.sourceforge.net to enable dumping out the modified XML\n* Support DIM\n", "description_content_type": "", "docs_url": null, "download_url": "", "downloads": { "last_day": -1, "last_month": -1, "last_week": -1 }, "home_page": "https://github.com/oddball/ipxact2systemverilog", "keywords": "ipxact2systemverilog ipxact2vhdl VHDL SystemVerilog html rst pdf IPXACT", "license": "GPL", "maintainer": "", "maintainer_email": "", "name": "ipxact2systemverilog", "package_url": "https://pypi.org/project/ipxact2systemverilog/", "platform": "", "project_url": "https://pypi.org/project/ipxact2systemverilog/", "project_urls": { "Homepage": "https://github.com/oddball/ipxact2systemverilog" }, "release_url": "https://pypi.org/project/ipxact2systemverilog/1.0.5/", "requires_dist": null, "requires_python": "", "summary": "Generate VHDL, SystemVerilog, html, rst, pdf from an IPXACT description", "version": "1.0.5" }, "last_serial": 3945823, "releases": { "1.0.0": [ { "comment_text": "", "digests": { "md5": "4fd846a5baae6929cdc51cad4104e325", "sha256": "9cdfc06c02796069bf7f33caccb911b39460a49822fd75fdfdb00654f5b62cf2" }, "downloads": -1, "filename": "ipxact2systemverilog-1.0.0.tar.gz", "has_sig": false, "md5_digest": "4fd846a5baae6929cdc51cad4104e325", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 43038, "upload_time": "2017-03-11T20:44:55", "url": "https://files.pythonhosted.org/packages/16/26/13ce2ee74240c8112e25f2bb55b78312461450135f6d906f83985237eef8/ipxact2systemverilog-1.0.0.tar.gz" } ], "1.0.0.dev0": [], "1.0.1": [ { "comment_text": "", "digests": { "md5": "d2c1249e84ba0745ebe872d10b7fbec1", "sha256": "a4e6bfdcdb3ecdc047ca8e56a01c2c5bfbb951b72fcef83546d7cd8c8f4c6132" }, "downloads": -1, "filename": "ipxact2systemverilog-1.0.1.tar.gz", "has_sig": false, "md5_digest": "d2c1249e84ba0745ebe872d10b7fbec1", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 43039, "upload_time": "2017-03-11T21:07:56", "url": "https://files.pythonhosted.org/packages/2d/dc/e6446a1572fb96f2cf9c5a074712b152bc7b9ea9d81dd034fb24c54d0e0e/ipxact2systemverilog-1.0.1.tar.gz" } ], "1.0.2": [ { "comment_text": "", "digests": { "md5": "5eff93e7416984932864fb49b68caf1f", "sha256": "62135e8377f73f03401870aa6bd2897b6203a2bdffcdbf7ae63ad8b19e107d3a" }, "downloads": -1, "filename": "ipxact2systemverilog-1.0.2.tar.gz", "has_sig": false, "md5_digest": "5eff93e7416984932864fb49b68caf1f", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 43273, "upload_time": "2017-08-19T15:34:24", "url": "https://files.pythonhosted.org/packages/1a/64/74ccb55498dd75489a231508415e556d0c410b48e26bdadc7fbab62ee9e1/ipxact2systemverilog-1.0.2.tar.gz" } ], "1.0.3": [ { "comment_text": "", "digests": { "md5": "0e5cf9f429b18bde45bd08b6fa1ab91b", "sha256": "cf7754a028ddb9bedbb679e2b7357ad48462a54373d9b54d3491ec9e30165c06" }, "downloads": -1, "filename": "ipxact2systemverilog-1.0.3.tar.gz", "has_sig": false, "md5_digest": "0e5cf9f429b18bde45bd08b6fa1ab91b", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 43325, "upload_time": "2017-12-14T20:20:51", "url": "https://files.pythonhosted.org/packages/fb/f5/4b4b7711ffd3c1d24ed2bba2395e0ebbb39338cfb3c780c9ea7ffc6723e2/ipxact2systemverilog-1.0.3.tar.gz" } ], "1.0.4": [ { "comment_text": "", "digests": { "md5": "d7d1ce62b79c1b858c76cde3127ed0af", "sha256": "5a344f93251f304666d4858ca2e05cdd130eda9f5672ef14e2540e9205d41e38" }, "downloads": -1, "filename": "ipxact2systemverilog-1.0.4.tar.gz", "has_sig": false, "md5_digest": "d7d1ce62b79c1b858c76cde3127ed0af", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 43366, "upload_time": "2017-12-18T21:31:06", "url": "https://files.pythonhosted.org/packages/af/24/25c809ec10974852c2314607de69e612abffa41dce0cc1fc2b536e60ed88/ipxact2systemverilog-1.0.4.tar.gz" } ], "1.0.5": [ { "comment_text": "", "digests": { "md5": "75a16d36adc0bd87795703462727cc57", "sha256": "a42c96b0c67e8cb9f2cabc9e39a57cb8a2dc168a590b0820f132f9a5f9aa730a" }, "downloads": -1, "filename": "ipxact2systemverilog-1.0.5.tar.gz", "has_sig": false, "md5_digest": "75a16d36adc0bd87795703462727cc57", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 43406, "upload_time": "2018-06-09T18:33:31", "url": "https://files.pythonhosted.org/packages/7b/6a/7620d02605d1783ff71cb2d69f539fbeb02653abdcda88a53940484f702a/ipxact2systemverilog-1.0.5.tar.gz" } ] }, "urls": [ { "comment_text": "", "digests": { "md5": "75a16d36adc0bd87795703462727cc57", "sha256": "a42c96b0c67e8cb9f2cabc9e39a57cb8a2dc168a590b0820f132f9a5f9aa730a" }, "downloads": -1, "filename": "ipxact2systemverilog-1.0.5.tar.gz", "has_sig": false, "md5_digest": "75a16d36adc0bd87795703462727cc57", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 43406, "upload_time": "2018-06-09T18:33:31", "url": "https://files.pythonhosted.org/packages/7b/6a/7620d02605d1783ff71cb2d69f539fbeb02653abdcda88a53940484f702a/ipxact2systemverilog-1.0.5.tar.gz" } ] }