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        "author": "Shinya Takamaeda-Yamazaki",
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        "description": "IPgen\n=====\n\nIP-core package generator for AXI4/Avalon\n\nCopyright (C) 2015, Shinya Takamaeda-Yamazaki\n\nE-mail: takamaeda_at_ist.hokudai.ac.jp\n\nLicense\n=======\n\nApache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)\n\nPublication\n===========\n\nIf you use IPgen in your research, please cite my paper about Pyverilog.\n(IPgen is constructed on Pyverilog.)\n\n-  Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design\n   Processing Toolkit for Verilog HDL, 11th International Symposium on\n   Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes\n   in Computer Science, Vol.9040/2015, pp.451-460, April 2015.\n   `Paper <http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42>`__\n\n::\n\n   @inproceedings{Takamaeda:2015:ARC:Pyverilog,\n   title={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL},\n   author={Takamaeda-Yamazaki, Shinya},\n   booktitle={Applied Reconfigurable Computing},\n   month={Apr},\n   year={2015},\n   pages={451-460},\n   volume={9040},\n   series={Lecture Notes in Computer Science},\n   publisher={Springer International Publishing},\n   doi={10.1007/978-3-319-16214-0_42},\n   url={http://dx.doi.org/10.1007/978-3-319-16214-0_42},\n   }\n\nWhat\u2019s IPgen?\n=============\n\nIPgen is a lightweight IP-core package synthesizer from abstract RTL\nsources. You can implement both AXI4 and Avalon IP-core by using the\nprovided abstract interfaces.\n\n-  ipgen_master_memory: memory-mapped access interface (master)\n-  ipgen_slave_memory: memory-mapped access interface (slave)\n-  ipgen_master_lite_memory: memory-mapped access lite interface\n   (master)\n-  ipgen_slave_lite_memory: memory-mapped access lite interface (slave)\n\nInstallation\n============\n\nRequirements\n------------\n\n-  Python3: 3.6 or later\n\n-  Icarus Verilog: 10.1 or later\n\n::\n\n   sudo apt install iverilog\n\n-  Jinja2: 2.10 or later\n-  Pyverilog: 1.1.3 or later\n\n::\n\n   pip3 install jinja2 pyverilog\n\nInstall\n-------\n\nInstall IPgen.\n\n::\n\n   python3 setup.py install\n\nGetting Started\n===============\n\nYou can use the ipgen command from your console.\n\n::\n\n   ipgen\n\nYou can find the sample projects in \u2018tests\u2019. Now let\u2019s see\n\u2018tests/memcpy\u2019. There is an input source code.\n\n-  memcpy.v : User-defined Verilog code using IPgen abstract memory\n   interfaces\n\nThen type \u2018make\u2019 and \u2018make run\u2019 to simulate sample system.\n\n::\n\n   make build\n   make sim\n\nOr type commands as below directly.\n\n::\n\n   ipgen default.config -t memcpy -I include tests/memcpy/memcpy.v\n   iverilog -I memcpy_ip_v1_00_a/hdl/verilog/ memcpy_ip_v1_00_a/test/test_memcpy_ip.v \n   ./a.out\n\nIPgen compiler generates a directory for IP-core (memcpy_ip_v1_00_a, in\nthis example).\n\n\u2018memcpy_ip_v1_00_a.v\u2019 includes - IP-core RTL design\n(hdl/verilog/memcpy_ip.v) - Test bench (test/test_memcpy_ip.v) - XPS\nsetting files (memcpy_ip_v2_1_0.{mpd,pao,tcl}) - IP-XACT file\n(component.xml)\n\nA bit-stream can be synthesized by using Xilinx Platform Studio, Xilinx\nVivado, and Altera Qsys. In case of XPS, please copy the generated\nIP-core into \u2018pcores\u2019 directory of XPS project.\n\nIPgen Command Options\n=====================\n\nCommand\n-------\n\n::\n\n   ipgen [config] [-t topmodule] [--ipname=ipname] [--memimg=memimg_name] [--usertest=usertest_name] [-I include]+ [-D define]+ [file]+\n\nDescription\n-----------\n\n-  config\n\n   -  System configuration file which includes memory and device\n      specifications\n\n-  -t\n\n   -  Top-module name of user logic, default: \u2018top\u2019\n\n-  \u2013-ipname\n\n   -  IP-core package name, default: \u2018(topmodule)_ip_(version)\u2019\n\n-  \u2013-memimg\n\n   -  Memory image file in HEX (option). The file is copied into test\n      directory. If no file is assigned, the array is initialized with\n      incremental values.\n\n-  \u2013-usertest\n\n   -  User-defined test code file (option). The code is copied into\n      testbench script.\n\n-  -I\n\n   -  Include path\n\n-  -D\n\n   -  Macro definition\n\n-  file\n\n   -  User-logic Verilog file (.v)\n\nRelated Project\n===============\n\n`Pyverilog <https://github.com/PyHDI/Pyverilog>`__ - Python-based\nHardware Design Processing Toolkit for Verilog HDL\n\n`Veriloggen <https://github.com/PyHDI/veriloggen>`__ - A library for\nconstructing a Verilog HDL source code in Python",
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        "keywords": "FPGA,Verilog HDL,IP-core,IP-XACT,AMBA AXI4,Avalon",
        "license": "Apache License 2.0",
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