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    "info": {
        "author": "Shinya Takamaeda-Yamazaki",
        "author_email": "shinya.takamaeda_at_gmail_com",
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        "description": "flipSyrup\r\n=========\r\n\r\nCycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms\r\n\r\nCopyright (C) 2013, Shinya Takamaeda-Yamazaki\r\n\r\nE-mail: shinya\\_at\\_is.naist.jp\r\n\r\nLicense\r\n=======\r\n\r\nApache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)\r\n\r\nWhat's flipSyrup?\r\n=================\r\n\r\nflipSyrup is an FPGA-based prototyping framework on modern FPGA\r\nplatforms.\r\n\r\nflipSyrup genrates an AXI4 IP-core package from your prototyping target\r\nRTL design implemented under the resource abstraction of FPGA platform\r\ngiven by flipSyrup. The generated IP-core can be used as a standard\r\nIP-core with other common IP-cores together.\r\n\r\nflipSyrup supports both single FPGA platform and multi-FPGA platform.\r\nYou can implement a cycle-accurate prototyping system on both\r\nsituations.\r\n\r\nflipSyrup employs two resources abstractions that an FPGA platform has.\r\n\r\n-  Syrup Memory\r\n\r\n   -  Memory system abstraction.\r\n   -  Prototyping target logic can use this abstract memory as an ideal\r\n      single-cycle memory.\r\n   -  flipSyrup compiler automatically synthesizes a cache-based memory\r\n      system to simulate cycle-accurately the taget behavior.\r\n\r\n-  Syrup Channel\r\n\r\n   -  Inter-FPGA interconnection abstraction for multi-FPGA platform\r\n      based prototyping.\r\n   -  Prototyping target logic can use this abstrct channel as a\r\n      register to be connected to its neighbor FPGA.\r\n   -  flipSyrup compiler automatically synthesizes a FIFO-based\r\n      synchronizatoin system to communicate with neighbor FPGAs.\r\n\r\nRequirements\r\n============\r\n\r\nSoftware\r\n--------\r\n\r\n-  Python (2.7 or later, 3.3 or later)\r\n-  Icarus Verilog (0.9.6 or later)\r\n-  'iverilog -E' command is used for the preprocessor.\r\n-  Jinja2 (2.7 or later)\r\n-  The code generator uses Jinja2 template engine.\r\n-  'pip install jinja2' (for Python 2.x) or 'pip3 install jinja2' (for\r\n   Python 3.x)\r\n\r\n-  Pyverilog (Python-based Verilog HDL Design Processing Toolkit) is\r\n   already included in this package.\r\n\r\nfor RTL simulation\r\n~~~~~~~~~~~~~~~~~~\r\n\r\n-  Icarus Verilog or Synopsys VCS\r\n-  Icarus Verilog is an open-sourced Verilog simulator\r\n-  VCS is a very fast commercial Verilog simulator\r\n\r\nFor synthesis of an FPGA circuit design (bit-file)\r\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\r\n\r\n-  Xilinx Platform Studio (14.6 or later)\r\n\r\n(Recommended) FPGA Board\r\n------------------------\r\n\r\nSingle FPGA Platform\r\n~~~~~~~~~~~~~~~~~~~~\r\n\r\n-  Digilent Atlys (Spartan-6)\r\n-  Xilinx ML605 (Virtex-6)\r\n-  Xilinx VC707 (Virtex-7)\r\n\r\nMulti-FPGA Platform\r\n~~~~~~~~~~~~~~~~~~~\r\n\r\n-  ScalableCore System (Spartan-6)\r\n\r\nInstallation\r\n============\r\n\r\nIf you want to use flipSyrup as a general library, you can install on\r\nyour environment by using setup.py.\r\n\r\nIf Python 2.7 is used,\r\n\r\n::\r\n\r\n    python setup.py install\r\n\r\nIf Python 3.x is used,\r\n\r\n::\r\n\r\n    python3 setup.py install\r\n\r\nThen you can use the flipSyrup command from your console (the version\r\nnumber depends on your environment).\r\n\r\n::\r\n\r\n    flipsyrup-0.8.0-py3.4.1\r\n\r\nGetting Started\r\n===============\r\n\r\nFirst, please make sure TARGET in 'base.mk' in 'input' is correctly\r\ndefined. If you use the installed pycoram command on your environment,\r\nplease modify 'TARGET' in base.mk as below (the version number depends\r\non your environment)\r\n\r\n::\r\n\r\n    TARGET=flipsyrup-0.8.0-py3.4.1\r\n\r\nYou can find the sample input projects in 'input/tests/singleport'.\r\n\r\n-  userlogic.v : User-defined Verilog code using Syrup memory blocks\r\n\r\nThen type 'make' and 'make run' to simulate sample system.\r\n\r\n::\r\n\r\n    make build\r\n    make sim\r\n\r\nOr type commands as below directly.\r\n\r\n::\r\n\r\n    python flipsyrup/flipsyrup.py input/sample.config -t userlogic -I include/ --usertest=input/tests/singleport/testbench.v input/tests/singleport/userlogic.v \r\n    iverilog -I syrup_userlogic_v1_00_a/hdl/verilog/ syrup_userlogic_v1_00_a/test/testbench_userlogic.v \r\n    ./a.out\r\n\r\nflipSyrup compiler generates a directory for IP-core\r\n(syrup\\_userlogic\\_v1\\_00\\_a, in this example).\r\n\r\n'syrup\\_userlogic\\_v1\\_00\\_a.v' includes \\* IP-core RTL design\r\n(hdl/verilog/syrup\\_userlogic.v) \\* Test bench\r\n(test/testbench\\_userlogic.v) \\* XPS setting files\r\n(syrup\\_userlogic\\_v2\\_1\\_0.{mpd,pao,tcl})\r\n\r\nA bit-stream can be synthesized by using Xilinx Platform Studio. Please\r\ncopy the generated IP-core into 'pcores' directory of XPS project.\r\n\r\nThis software has some sample project in 'input'. To build them, please\r\nmodify 'Makefile', so that the corresponding files and parameters are\r\nselected (especially INPUT, MEMIMG and USERTEST)\r\n\r\nflipSyrup Command Options\r\n=========================\r\n\r\nCommand\r\n-------\r\n\r\n::\r\n\r\n    python flipsyrup.py [config] [-t topmodule] [-I includepath]+ [--memimg=filename] [--usertest=filename] [file]+\r\n\r\nDescription\r\n-----------\r\n\r\n-  file\r\n\r\n   -  User-logic Verilog file (.v) and FPGA system memory specification\r\n      (.config). Automatically, .v file is recognized as a user-logic\r\n      Verilog file, and .config file recongnized as a memory\r\n      specification of used FPGA system, respectively.\r\n\r\n-  config\r\n\r\n   -  Configuration file which includes memory and device specification\r\n\r\n-  -t\r\n\r\n   -  Name of user-defined top module, default is \"userlogic\".\r\n\r\n-  -I\r\n\r\n   -  Include path for input Verilog HDL files.\r\n\r\n-  --memimg\r\n\r\n   -  DRAM image file in HEX DRAM (option, if you need). The file is\r\n      copied into test directory. If no file is assigned, the array is\r\n      initialized with incremental values.\r\n\r\n-  --usertest\r\n\r\n   -  User-defined test code file (option, if you need). The code is\r\n      copied into testbench script.\r\n\r\nPublication\r\n===========\r\n\r\n-  Shinya Takamaeda-Yamazaki and Kenji Kise: flipSyrup: Cycle-Accurate\r\n   Hardware Simulation Framework on Abstract FPGA Platforms, 24th\r\n   International Conference on Field Programmable Logic and Applications\r\n   (FPL 2014) (Poster), September 2014.\r\n\r\nRelated Project\r\n===============\r\n\r\n`Pyverilog <http://shtaxxx.github.io/Pyverilog/>`__ - Python-based\r\nHardware Design Processing Toolkit for Verilog HDL - Used as basic code\r\nanalyser and generator",
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        "keywords": "FPGA,Verilog HDL,Memory System Abstraction,IP-core,AMBA AXI4, FPGA-based Rapid Prototyping, Cycle-Accurate Simulation",
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