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        "author": "Leonard Truong",
        "author_email": "lenny@cs.stanford.edu",
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        "description": "# Fault\n[![Build Status](https://travis-ci.com/leonardt/fault.svg?branch=master)](https://travis-ci.com/leonardt/fault)\n[![Coverage Status](https://coveralls.io/repos/github/leonardt/fault/badge.svg?branch=master)](https://coveralls.io/github/leonardt/fault?branch=master)\n\nA Python package for testing hardware (part of the magma ecosystem).\n\n[API Documentation](http://truong.io/fault/)\n\n[CHANGELOG](./CHANGELOG.md)\n\n## Installation\n```\npip install fault\n```\n\n## Documentation\nCheck out the [fault tutorial](https://github.com/leonardt/fault/tree/master/tutorial)\n\n* [Actions](https://github.com/leonardt/fault/blob/master/doc/actions.md)\n* [Tester](https://github.com/leonardt/fault/blob/master/doc/tester.md)\n* [Integrating External Verilog](https://github.com/leonardt/fault/blob/master/doc/verilog_integration.ipynb)\n\n## Example\nHere is a simple ALU defined in magma.\n```python\nimport magma as m\nimport mantle\n\n\nclass ConfigReg(m.Circuit):\n    IO = [\"D\", m.In(m.Bits(2)), \"Q\", m.Out(m.Bits(2))] + \\\n        m.ClockInterface(has_ce=True)\n\n    @classmethod\n    def definition(io):\n        reg = mantle.Register(2, has_ce=True, name=\"conf_reg\")\n        io.Q <= reg(io.D, CE=io.CE)\n\n\nclass SimpleALU(m.Circuit):\n    IO = [\"a\", m.In(m.UInt(16)),\n          \"b\", m.In(m.UInt(16)),\n          \"c\", m.Out(m.UInt(16)),\n          \"config_data\", m.In(m.Bits(2)),\n          \"config_en\", m.In(m.Enable),\n          ] + m.ClockInterface()\n\n    @classmethod\n    def definition(io):\n        opcode = ConfigReg(name=\"config_reg\")(io.config_data, CE=io.config_en)\n        io.c <= mantle.mux(\n            [io.a + io.b, io.a - io.b, io.a * io.b, io.a / io.b], opcode)\n```\n\nHere's an example test in fault that uses the configuration interface, expects\na value on the internal register, and checks the result of performing the\nexpected operation.\n\n```python\nimport operator\nimport fault\n\nops = [operator.add, operator.sub, operator.mul, operator.floordiv]\ntester = fault.Tester(SimpleALU, SimpleALU.CLK)\ntester.circuit.CLK = 0\ntester.circuit.config_en = 1\nfor i in range(0, 4):\n    tester.circuit.config_data = i\n    tester.step(2)\n    tester.circuit.a = 3\n    tester.circuit.b = 2\n    tester.eval()\n    tester.circuit.c.expect(ops[i](3, 2))\n```\n\nWe can run this with three different simulators\n\n```python\ntester.compile_and_run(\"verilator\", flags=[\"-Wno-fatal\"], directory=\"build\")\ntester.compile_and_run(\"system-verilog\", simulator=\"ncsim\", directory=\"build\")\ntester.compile_and_run(\"system-verilog\", simulator=\"vcs\", directory=\"build\")\n```\n\n### Working with internal signals\nFault supports peeking, expecting, and printing internal signals. For the\n`verilator` target, you should use the keyword argument `magma_opts` with\n`\"verilator_debug\"` set to true.  This will cause coreir to compile the verilog\nwith the required debug comments.  Example:\n```python\ntester.compile_and_run(\"verilator\", flags=[\"-Wno-fatal\"], \n                       magma_opts={\"verilator_debug\": True}, directory=\"build\")\n```\n\nIf you're using `mantle.Register` from the `coreir` implementation, you can\nalso poke the internal register value directly using the `value` field.  Notice\nthat `conf_reg` is defined in `ConfigReg` to be an instance of\n`mantle.Register` and the test bench pokes it by setting `confg_reg.value`\nequal to `1`.\n\n```python\ntester = fault.Tester(SimpleALU, SimpleALU.CLK)\ntester.circuit.CLK = 0\n# Set config_en to 0 so stepping the clock doesn't clobber the poked value\ntester.circuit.config_en = 0\n# Initialize\ntester.step(2)\nfor i in reversed(range(4)):\n    tester.circuit.config_reg.conf_reg.value = i\n    tester.step(2)\n    tester.circuit.config_reg.conf_reg.O.expect(i)\n    # You can also print these internal signals using the getattr interface\n    tester.print(\"O=%d\\n\", tester.circuit.config_reg.conf_reg.O)\n```\n\n## FAQ\n\n### How do I generate waveforms with fault?\n\nFault supports generating `.vcd` dumps when using the `verilator` and\n`system-verilog/ncsim` target.\n\nFor the `verilator` target, use the `flags` keyword argument to pass the\n`--trace` flag.  For example,\n\n    tester.compile_and_run(\"verilator\", flags=[\"-Wno-fatal\", \"--trace\"])\n\nThe `--trace` flag must be passed through to verilator so it generates code\nthat supports waveform dumping. The test harness generated by fault will\ninclude the required logic for invoking `tracer->dump(main_time)` for every\ncall to `eval` and `step`.  `main_time` is incremented for every call to step.\nThe output `.vcd` file will be saved in the file `logs/{circuit_name}` where\n`circuit_name` is the name of the ciruit passed to `Tester`.  The `logs`\ndirectory will be placed in the same directory as the generated harness, which\nis controlled by the `directory` keyword argument (by default this is\n`\"build/\"`).\n\nFor the `system-verilog/ncsim` target, tracing is enabled by default. For\n`ncsim`, the trace will be placed in a file called `verilog.vcd` in the same\ndirectory as the generated harness.",
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