{ "info": { "author": "Clifford Wolf", "author_email": "clifford@clifford.at", "bugtrack_url": null, "classifiers": [], "description": "Chipy -- Constructing Hardware In PYthon\n========================================\n\nChipy is a single-file python module for generating digital hardware. Chipy\nprovides a simple and clean API for writing Verilog code generators. Structural\nand behavioral circuit modelling is supported.\n\n\nA Simple Example\n================\n\nThe following is a simple Chipy example design:\n\n from Chipy import *\n\n with AddModule(\"ADD_OR_SUB_DEMO\"):\n clk = AddInput(\"CLK\")\n sub = AddInput(\"SUB\")\n a, b = AddInput(\"A B\", 32)\n out = AddOutput(\"OUT\", 32, posedge=clk)\n\n with If(sub):\n out.next = a - b\n with Else:\n out.next = a + b\n\n with open(\"demo.v\", \"w\") as f:\n WriteVerilog(f)\n\nThe `AddModule` function adds a new module to the design and return it. To\nadd elements to a module, create a `with : ...` block and call the\ncorresponding `Add...` functions from within that block.\n\nMany functions and expressions in Chipy code return a *signal*. E.g.\n`AddInput(..)`, `AddOutput(..)`, or `a + b` in the above code. Some\nsignals are *registers*, which just means that they can be assigned\nto, either by calling `Assign(, )` or by assigning\nto the `.next` attribute, as demonstrated in the code above.\n\nRegisters also need a synchronisation element, such as a FF, assigned to them.\nThis can either be done by calling functions such as `AddFF(..)`, or in simple\ncases using keyword arguments such as `posedge=` when creating\nthe register itself.\n\nRegisters that are not assigned a value and/or do not have a synchronization\nelement will cause a runtime error in `WriteVerilog`.\n\nFinally assignments can be conditional, enabling behavioral modelling. This is\ndone by putting the assignments in blocks such as `with If(..): ...` or\n`with Else:`.\n\nHere is a different version of the design, demonstrating some of the variations\nmentioned so far:\n\n from Chipy import *\n\n with AddModule(\"ADD_OR_SUB_DEMO\"):\n clk = AddInput(\"CLK\")\n sub = AddInput(\"SUB\")\n a, b = AddInput(\"A B\", 32)\n out = AddOutput(\"OUT\", 32)\n\n with If(sub):\n Assign(out, a - b)\n with Else:\n Assign(out, a + b)\n\n\tAddFF(out, posedge=clk)\n\n with open(\"demo.v\", \"w\") as f:\n WriteVerilog(f)\n\n\nChipy Reference Manual\n======================\n\nChipy maintains a global design state that contains a set of (Verilog/RTL)\nmodules and a stack of design contexts. The Chipy `Add*` functions are used to\nadd elements to the design in memory. Chipy APIs that are used with the Python\n`with` statement are used to maintain the stack of design contexts. The current\ncontext determines for example to which module a new instance or wire should be\nadded. So for example, the `AddInput` function does not have a parameter that\ntells it to which module to add a new input port. Instead the input port is\nadded to the module referenced to by the current context.\n\n\nCreating modules and generating Verilog\n---------------------------------------\n\n### AddModule(name)\n\nThis function adds a new module to the design. The module created by this function\nis returned. A Python `with` block using a Chipy module as argument is used to\ncreate a new Chipy context that can be used to add elements to the module. For\nexample, the following will create a new module `demo` with an input port `clk`:\n\n demo_mod = AddModule(\"demo\")\n\n with demo_mod:\n AddInput(\"clk\")\n\n### Module(name=None)\n\nThis functions looks up the module with the specified name. If no such module\nis found, `None` is returned. If the name parameter is omitted then the module\nreferenced by the current context is returned.\n\n### WriteVerilog(f)\n\nThis function write the current design to the specified file handle. The file\nhas to be opened first using for example the Python `open` function:\n\n with open(\"demo.v\", \"w\") as f:\n WriteVerilog(f)\n\n### ResetDesign()\n\nThis function resets the global Chipy state, e.g. for when multiple designs are\ncreated from one Python script.\n\n\nAdding inputs and outputs\n-------------------------\n\n### AddInput(name, type=1)\n\nThis function adds a new input port to the current module. The new signal is\nreturned. If name contains more than one white-space separated token, then\nmultiple ports are created at once and a list is returned. For example:\n\n with AddModule(\"demo\"):\n clk, a, b = AddInput(\"clk a b\")\n\nThe `type` argument specifies the width of the new signal. A negative number\ndenotes a signed signal, i.e. the value `5` would be used to create an unsigned\n5 bit wide signal, and the value `-5` would be used to create a signed 5 bit\nwide signal.\n\nInstead of an integer, an *interface* (see below) can be passed as `type` for\nthe new signal. In that case multiple input ports are generated, as specified by\nthe interface, and a *bundle* (see blow) of those signals is returned.\n\n### AddOutput(name, type=1, posedge=None, negedge=None, nodefault=False, async=False)\n\nLike `AddInput`, but adds and output port. The signals returned by this functions\nare *registers*, i.e. they have a `.next` member that can be assigned to.\n\nThe keyword arguments `posedge`, `negedge`, and `nodefault` cause `AddOuput` to\nautomatically call `AddFF` (see below) on the generated registers. Similarly,\n`async=True` causes `AddOuput` to call `AddAsync` (see below) on the generated\nregisters.\n\nRegisters and synchronization elements\n--------------------------------------\n\n### AddReg(name, type=1, posedge=None, negedge=None, nodefault=False, async=None)\n### AddFF(signal, posedge=None, negedge=None, nodefault=False)\n### AddAsync(signal)\n### Assign(lhs, rhs)\n\nSignals and expessions\n----------------------\n\n### Sig(arg, width=None)\n### Sig Operators\n### Cond(cond, if\\_val, else\\_val)\n### Concat(args)\n### Repeat(num, sig)\n\nBundles\n-------\n\n### Bundle(arg=None, \\*\\*kwargs)\n### Bundle.add(self, name, member)\n### Bundle.get(name)\n### Bundle.regs() and Bundle.regs()\n### Bundle.keys(), Bundle.values(), Bundle.items()\n### Zip(bundles, recursive=False)\n### Module.bundle(self, prefix=\"\")\n\nInterfaces\n----------\n\n### AddPort(name, type, role, posedge=None, negedge=None, nodefault=False, async=None)\n### Module.intf(self, prefix=\"\")\n### Stream(data\\_type, last=False, destbits=0)\n\nMemories\n--------\n\n### AddMemory(name, type, depth, posedge=None, negedge=None)\n### Memory read and write\n### Memory bundles\n\nHierarchical Designs\n--------------------\n\n### AddInst(name, type)\n### Connect(sigs)\n\nBehavioral Modelling\n--------------------\n\n### If, ElseIf, Else\n### Switch, Case, Default\n\nTodos\n=====\n\n- Complete documentation\n- More testcases / examples\n- Improved error reporting\n- Bundles: flat, unflat, Map, concat\n- Verilog Primitive Inst\n- Backbox modules\n- Label(name, sig)\n\nLicense\n=======\n\nChipy -- Constructing Hardware In PYthon\n\nCopyright (C) 2016 Clifford Wolf \n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.", "description_content_type": "", "docs_url": null, "download_url": "", "downloads": { "last_day": -1, "last_month": -1, "last_week": -1 }, "home_page": "https://github.com/chipy-hdl/chipy", "keywords": "eda,cad,hdl,verilog", "license": "ISC", "maintainer": "", "maintainer_email": "", "name": "chipy", "package_url": "https://pypi.org/project/chipy/", "platform": "", "project_url": "https://pypi.org/project/chipy/", "project_urls": { "Homepage": "https://github.com/chipy-hdl/chipy" }, "release_url": "https://pypi.org/project/chipy/0.1.1/", "requires_dist": null, "requires_python": "", "summary": "Chipy is a single-file python module for generating digital hardware.", "version": "0.1.1" }, "last_serial": 3722087, "releases": { "0.1.1": [ { "comment_text": "", "digests": { "md5": "8deee036e3549310c2b1341840ade4b0", "sha256": "b545aa6242e482937e7265dabf098b11e6d109acc56aafcdf6a6ec52ab489868" }, "downloads": -1, "filename": "chipy-0.1.1.tar.gz", "has_sig": false, "md5_digest": "8deee036e3549310c2b1341840ade4b0", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 11241, "upload_time": "2018-03-31T12:41:20", "url": "https://files.pythonhosted.org/packages/58/8c/7f94186058a7a913d526f7448b682c9e2693c0c8ad778d7df738beb53f27/chipy-0.1.1.tar.gz" } ] }, "urls": [ { "comment_text": "", "digests": { "md5": "8deee036e3549310c2b1341840ade4b0", "sha256": "b545aa6242e482937e7265dabf098b11e6d109acc56aafcdf6a6ec52ab489868" }, "downloads": -1, "filename": "chipy-0.1.1.tar.gz", "has_sig": false, "md5_digest": "8deee036e3549310c2b1341840ade4b0", "packagetype": "sdist", "python_version": "source", "requires_python": null, "size": 11241, "upload_time": "2018-03-31T12:41:20", "url": "https://files.pythonhosted.org/packages/58/8c/7f94186058a7a913d526f7448b682c9e2693c0c8ad778d7df738beb53f27/chipy-0.1.1.tar.gz" } ] }