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    "info": {
        "author": "Ben Reynwar",
        "author_email": "ben@reynwar.net",
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        "description": ".. image:: https://travis-ci.org/benreynwar/axilent.svg?branch=master\n               :target: https://travis-ci.org/benreynwar/axilent\n\naxilent\n=======\n\naxilent provides python tools for describing a sequence of Axi4Lite command\nin python.\n\nA python test can be written describing the sequence of commands to be sent\nand the expected responses.  This test can then be run against both a\nsimulation of the design and against the implemented design running on an\nFPGA.\n\naxilent is structured so that tests can be run both against both interactive\nsimulations and simulations where inputs cannot depend on outputs such as\nfile-based testbenchs.\n\n\nHandlers\n--------\n\nCurrently there is `handler` for working with file-based testbenchs\ngenerated by `slvcodec <https://github.com/benreynwar/slvcodec>`_ and\nfor simulations on FPGAs run over JTAG using\n`pyvivado <https://github.com/benreynwar/pyvivado>`_.\nIn the likely event you are using neither of these methods, then you\nwill have to write you own handler. The handler has a single required\nmethod.\n\nhandler.send(command)\n    Sends a command to the FPGA, or adds the command to the list of commands that\n    will be run in the simulation.\n\nThe handler also processes the responses from the simulation or FPGA and updates the\n`command.future` values appropriately.  It calls the `command.process_responses` method\nto help process the responses.\n\n\nCommands\n--------\nA `Command` object represents a simple axi4lite read or write, or a more complex\naggregrate consisting of many read and write commands.\n\ncommand.get_axi_commands()\n    Returns a list of `AxiCommand` objects.  Each `AxiCommand` object is a simple\n    axi4lite read or write command to a single address or a range of addresses.\n\ncommand.process_responses(read_responses, write_responses, resolve_future)\n    Processes two lists of `AxiResponse` objects, one is a list of responses to\n    write requests and one is a list of responses to read requests.  The two lists\n    must begin with the responses to this command, and these entries are removed\n    from the lists.\n    An (exception, result) tuple is returned by the function.  If `resolve_future`\n    is True then the commands future is resolved with the result and exception.\n\nAs an example consider an AxiAdder module, which uses an Axi4Lite interface.  We can\nwrite to registers A and B, and when we read from register C the returned result is\nthe sum of the contents in regsiters A and B.  We can create a `Command` object to\nrepresent using this hardware to add two numbers.\n\n.. code:: python\n\n    class AddNumbersCommand(comms.CombinedCommand):\n        '''\n        A command that writes to the intA and intB registers\n        and then reads from the intC register.\n        The effect is the add the two inputs.\n        '''\n\n        def __init__(self, a, b, addresses):\n            write_a_command = comms.SetUnsignedCommand(\n                address=addresses['intA'], value=a,\n                description='Setting A in AddNumbers',\n            )\n            write_b_command = comms.SetUnsignedCommand(\n                address=addresses['intB'], value=b,\n                description='Setting B in AddNumbers',\n            )\n            read_c_command = comms.GetUnsignedCommand(\n                address=addresses['intC'],\n                description='Getting C from AddNumbers',\n            )\n            commands = (write_a_command, write_b_command, read_c_command)\n            super().__init__(\n                description='Add 2 numbers with AddNumber',\n                commands=commands)\n\n        def process_responses(self, read_responses, write_responses, resolve_future=True):\n            '''\n            Return the third response (from the final read command)\n            Don't return any errors.\n            '''\n            e, result = super().process_responses(read_responses, write_responses, resolve_future=False)\n            intc = result[2]\n            if resolve_future:\n                self.resolve_future(e, intc)\n            return e, intc\n\n\n\nComm\n----\nTypically command objects are hidden from the testing interface by wrapping them\nwith a Comm object.  Methods on this comm object create `Command` objects, send\nthem to a handler, and return the command futures.\n\n.. code:: python\n\n    class AxiAdderComm:\n        '''\n        Class to communicate with the AxiAdder module.\n        '''\n\n        INTA_ADDRESS = 0\n        INTB_ADDRESS = 1\n        INTC_ADDRESS = 2\n\n        def __init__(self, address_offset, handler):\n            '''\n            `address_offset` is any addition that is made to the address that is\n            consumed during routing.\n            `handler` is the object responsible for dispatching the commands.\n            '''\n            self.handler = handler\n            self.address_offset = address_offset\n            self.addresses = {\n                'intA': address_offset + self.INTA_ADDRESS,\n                'intB': address_offset + self.INTB_ADDRESS,\n                'intC': address_offset + self.INTC_ADDRESS,\n            }\n\n        def add_numbers(self, a, b):\n            '''\n            A complex complex command that write to two registers and\n            then reads from another.\n            Sets 'a' and 'b' then reads 'c' (should be a+b)\n            '''\n            command = AddNumbersCommand(a, b, self.addresses)\n            self.handler.send(command)\n            return command.future\n\nTests\n-----\nA possible way to write a test to is define a class with a `prepare` method that\ndefines the requests to send to the module, and a `check` method that analyzes\nthe responses.\n\nThe `prepare` method uses a `handler` to generate the requests and creates a\nnumber of futures to hold the results of processing the responses.\n\nThe responses are then processed by a handler-dependent method and then the\n`check` method can be run to check the contents of the resolved futures.\n\n.. code:: python\n\n    class AxiAdderTest(object):\n\n        def __init__(self):\n            self.expected_intcs = []\n            self.intc_futures = []\n\n        def prepare(self, handler):\n            '''\n            Sends a number of 'add_numbers' commands.\n            '''\n            comm = AxiAdderComm(address_offset=0, handler=handler)\n            n_data = 20\n            max_int = pow(2, 16)-1\n            logger.debug('preparing data')\n            for i in range(n_data):\n                inta = random.randint(0, max_int)\n                intb = random.randint(0, max_int)\n                self.expected_intcs.append(inta + intb)\n                future = comm.add_numbers(inta, intb)\n                self.intc_futures.append(future)\n            # Flush the communication for simulations.\n            # Ignored in FPGA.\n            handler.send(comms.FakeWaitCommand(clock_cycles=10))\n\n        def check(self):\n            '''\n            Check that the output of the commands matches the expected values.\n            '''\n            output_intcs = [f.result() for f in self.intc_futures]\n            assert output_intcs == self.expected_intcs\n            print('Success!!!!!!!!!!!!!!!')\n\n\n\nRepeatability of Simulations\n----------------------------\nAlthough the simulations are repeatable the FPGA-based tests are currently not\nrepeatable because of the changing number of clock-cycles between when requests\nare received.\nI would like to fix this by allowing the ability of specify on which clock\ncycle at AXI request should be sent (they would be gathered in a delayed in a buffer\non the FPGA until the correct clock cycle).\nTODO: Add delaying of requests to allow repeatability.\n\n\n",
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        "keywords": "VHDL,hdl,rtl,FPGA,ASIC,Xilinx,Altera",
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